How to obtain original input/output signal name from SDF Timing Simulation within Modelsim?

Discussion in 'VHDL' started by Chao, Jun 10, 2004.

  1. Chao

    Chao Guest

    Hi, there

    I am dealing with the back-annotated SDF timing simulation. The
    timing_vhdl file is generated by the Xilinx ISE tool and I applied it
    to the Modelsim simulator. But how can I obtain my original
    input/output signal? With older tools, I can identify, for instance,
    ...._D is the input of Data FF, ..._Q is the output of Data FF. But now
    I cannot trace these signals any more. It is dissappeard. How can I
    work around this problem? Which abbreviate is short for input or
    output of data flip-flop? I would appreciate any idea and suggestions.
    Thanks.

    Chao.
     
    Chao, Jun 10, 2004
    #1
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  2. (Chao) wrote in message news:<>...

    > I am dealing with the back-annotated SDF timing simulation. The
    > timing_vhdl file is generated by the Xilinx ISE tool and I applied it
    > to the Modelsim simulator. But how can I obtain my original
    > input/output signal?


    Maybe you are using a component instance,
    and need a configuration.
    Here's an example:
    ____________________________________________
    -- vital entity by place+route
    -- vho = /usr0/tres/vhdl/xszero/synth/work
    configuration vital of test_xszero is
    for sim
    for dut:socket
    use entity vho.xszero(\ep1k50fc256-1\);
    end for;
    end for;
    end configuration vital;
    ______________________________________________

    Or maybe you haven't written a vhdl testbench yet.
    It is signals from the testbench architecture.
    that drive your design instance.

    -- Mike Treseler
     
    Mike Treseler, Jun 11, 2004
    #2
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  3. Chao

    ALuPin Guest

    When simulating .sdf in Modelsim, I can see the registered signal names
    of my VHDL description apart from many other gate level names.

    Should I not be able to see the "original" registered names?

    Thank you.

    Kind regards
     
    ALuPin, Jun 14, 2004
    #3
  4. Chao

    Chao Guest

    At first thanks for Mike's answer. But my exact question was how to
    extract so many many internal signals which are listed during the
    timing simulation. For example, _inbuf, _ibuf, _gst, etc. How can I
    know which signal represents my original input signal or output
    signal?

    (Mike Treseler) wrote in message news:<>...
    > (Chao) wrote in message news:<>...
    >
    > > I am dealing with the back-annotated SDF timing simulation. The
    > > timing_vhdl file is generated by the Xilinx ISE tool and I applied it
    > > to the Modelsim simulator. But how can I obtain my original
    > > input/output signal?

    >
    > Maybe you are using a component instance,
    > and need a configuration.
    > Here's an example:
    > ____________________________________________
    > -- vital entity by place+route
    > -- vho = /usr0/tres/vhdl/xszero/synth/work
    > configuration vital of test_xszero is
    > for sim
    > for dut:socket
    > use entity vho.xszero(\ep1k50fc256-1\);
    > end for;
    > end for;
    > end configuration vital;
    > ______________________________________________
    >
    > Or maybe you haven't written a vhdl testbench yet.
    > It is signals from the testbench architecture.
    > that drive your design instance.
    >
    > -- Mike Treseler
     
    Chao, Jun 14, 2004
    #4
  5. Re: How to obtain original input/output signal name from SDF TimingSimulation within Modelsim?

    Chao wrote:
    > At first thanks for Mike's answer. But my exact question was how to
    > extract so many many internal signals which are listed during the
    > timing simulation. For example, _inbuf, _ibuf, _gst, etc. How can I
    > know which signal represents my original input signal or output
    > signal?


    The job of synthesis is to create a netlist of primitives
    (like dffe, inbuf etc. ) that sims the same as your code.
    You can view the netlist on tools like leonardo.
    I don't know of any way to relate primitives to your
    source code.

    Normally synthesis "just works".
    When it doesn't consider the following.

    1. Double check the static timing report and synthesis warnings.
    2. Eliminate asynchronous processes and multiple clocks.
    3. Double check all inputs for synchronization.
    4. Break the design into pieces zoom in on the problem.

    Good luck,

    -- Mike Treseler
     
    Mike Treseler, Jun 14, 2004
    #5
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