How to print std_logic_vector variable into hex string in VHDL

Discussion in 'VHDL' started by Carson, Aug 31, 2005.

  1. Carson

    Carson Guest

    Hi,

    How to print std_logic_vector variable into hex string in VHDL?

    Thanks,

    Carson
     
    Carson, Aug 31, 2005
    #1
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  2. Carson

    Niv Guest


    > How to print std_logic_vector variable into hex string in VHDL?
    >


    Forgotten the exact syntax & textbook not to hand, but something like:

    use std.textio

    and then use:

    HWRITE (myline, signame);
    WRITELINE (myfile, myline);
    where signame is your std_log_vec.

    Niv.
     
    Niv, Aug 31, 2005
    #2
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  3. Mike Treseler, Aug 31, 2005
    #3
  4. Carson

    Carson Guest

    Thanks,

    Is there any command like "report integer'image(myvalue)"; so that it
    will print out hex?
     
    Carson, Sep 1, 2005
    #4
  5. Carson

    David Bishop Guest

    Mike Treseler wrote:
    > Carson wrote:
    >
    >> How to print std_logic_vector variable into hex string in VHDL?

    >
    >
    > Here's one way:
    > http://home.comcast.net/~mike_treseler/print_vec.vhd


    Here's another:

    http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/std_logic_1164_additions.vhd

    The function is called "to_hstring", it works like this:

    report "The string was " & to_hstring (slvec)

    There is also a "to_string" and "to_ostring" function in this package,
    which containts all of the additions we plan to make to std_logic_1164
    in VHDL-2006.
     
    David Bishop, Sep 1, 2005
    #5
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