how to read jpg file using VHDL

[raj]

i want VHDL code of reading an image....and view that image after
processing.......with explaination.....i know about TEXTIO
package.......but how to use that.....??

 

[Tricky]

i want VHDL code of reading an image....and view that image after
processing.......with explaination.....i know about TEXTIO
package.......but how to use that.....??

First you will need to read the file in character by character. you
dont even need textio. It can be done like this:

type data_file_t is file of character;
file my_file : data_file_t open READ_MODE is "<path>";
variable c_buf : character;
variable my_int : integer;

then you can read the characters in by using:

read(my_file, c_buf);

You then have a single character. you can convert this to an integer
by:

my_int := character'pos(c_buf).

Now, thats the easy bit. The tricky bit is going to be reading the jpg
file header to determin how big your storage array needs to be, and
you'll probably have to use pointers. It then gets even trickier as
you have to write functions to uncompress the jpg data. you will have
to google that.

I suggest you convert your JPGs into bitmaps as they are alot easier
to read as the data is uncompressed and can be read directly. For an
explination of the BMP file header, see here:

http://www.fortunecity.com/skyscraper/windows/364/bmpffrmt.html

But overall, VHDL is not really designed for easy file IO. It provides
useful textio functions, and binary fileIO can be done with a bit of a
work around (as shown), but there are no APIs for doing anything you
could easily do in software (like read a jpg file). So you either have
to write the functions in VHDL yourself, or convert the files
externally to something more useful.

 

[raj]

Since a JPG image is not a text file, forget about std.textio.

VHDL can be used for reading and writing binary files; a little
searching online will show examples to get you started.

Then you need to understand the file format of .jpg files, and write a
parser for that format. Again, there will be documentation available. If
you are lucky, you may not need to support all variations of the format;
e.g. if you only need to read a few images for demonstration.

If you are more comfortable programming in another language you may want
to test your understanding of the JPG format by writing a JPG image
decoder in that other language first, and using it as the basis for your
VHDL design.

Alternatively, there are much simpler file formats than .jpg. For
example, .bmp images would be much easier to read and write, if the
image processing is the important part of your project rather than the
JPEG decoding.

Also be aware that binary file I/O in VHDL is not guaranteed to be
portable between simulators. In Modelsim it just works as you would
expect (and you can easily read and write standard file formats).
However Xilinx ISE Simulator has its own file format. It can read files
it has written, but they are not in the same format as any other files.
To read a JPG file in this simulator you would need to convert it into
ISIM's file format (which has an eight byte header, and opposite
endian-ness to the host system). Good luck getting documentation on this
format from Xilinx (I've had a Webcase open for 5 weeks so far)
Other simulators may be different again.

- Brian

actually i want to implement my algorithms on virtex 5...so.....for
that..what to do.....what changes required in vhdl
programs.....because as i know...architecture of virtex 5 is little
bit different.....than others FPGA....

i have another problem.............i have to implement 8 point FFT on
virtex 5.......i have complete software part but problem coming in
implementation part on virtex 5....not getin how to assign proper pin
number to make UCF file...how to give inputs through hex editor........

 

[Tricky]

actually i want to implement my algorithms on virtex 5...so.....for
that..what to do.....what changes required in vhdl
programs.....because as i know...architecture of virtex 5 is little
bit different.....than others FPGA....

i have another problem.............i have to implement 8 point FFT on
virtex 5.......i have complete software part but problem coming in
implementation part on virtex 5....not getin how to assign proper pin
number to make UCF file...how to give inputs through hex editor........

In that case, forget everything everyone else has posted, and also
forget about textio. Textio and file reading in VHDL is for
testbenching only, and not synthesizable.

 

[raj]

then what to do.....sir............?

In that case, forget everything everyone else has posted, and also
forget about textio. Textio and file reading in VHDL is for
testbenching only, and not synthesizable.

 

[raj]

then what to do..sir,,,,,?

In that case, forget everything everyone else has posted, and also
forget about textio. Textio and file reading in VHDL is for
testbenching only, and not synthesizable.

 

[Mike Treseler]

If you want synthesis code, you can

1. learn vhdl simulation and synthesis and write your own.
2. buy a core.
3. hire a consultant.

actually i want to implement my algorithms on virtex 5...so.....for
that..what to do.....what changes required in vhdl

Changes?

If you have vhdl sources already,
just edit and sim until it works.

-- Mike Treseler

 

[raj]

If you want synthesis code, you can

  1. learn vhdl simulation and synthesis and write your own.
  2. buy a core.
  3. hire a consultant.


Changes?

If you have vhdl sources already,
just edit and sim until it works.

      -- Mike Treseler

8 point FFT prog has already simulated.......but my problem is..how to
implement it on vietex 5.....how to give inputs to get proper
output......through hex editor.....in xilinx 9.....there is any option
of hex editor.........?????????

 

[Tricky]

8 point FFT prog has already simulated.......but my problem is..how to
implement it on vietex 5.....how to give inputs to get proper
output......through hex editor.....in xilinx 9.....there is any option
of hex editor.........?????????

A virtex 5, or any FPGA, is not a processor. It is whatever you want
it to be, but sending it data is not as simple as you are thinking.
You have to design the core you want to put in there, which includes
the processor and whatever communication method you want.

From what you are posting it sounds like you think the virtex 5 is
more than a blank canvas. There is no method of communication with the
Virtex 5 other than the one you put there yourself. When you say you
have done simulation already, is this software simulation, or VHDL
simulation? Do you have a VHDL version of your FFT core?

 

[rajashree.SMST]

A virtex 5, or any FPGA, is not a processor. It is whatever you want
it to be, but sending it data is not as simple as you are thinking.
You have to design the core you want to put in there, which includes
the processor and whatever communication method you want.

From what you are posting it sounds like you think the virtex 5 is
more than a blank canvas. There is no method of communication with the
Virtex 5 other than the one you put there yourself. When you say you
have done simulation already, is this software simulation, or VHDL
simulation? Do you have a VHDL version of your FFT core?

i am using xilinx ISE 9 (VHDL) and modelslim........my program has
synthesized...but my problem is.. i did not understand..how to
implement it ..

i think.....still i have some conceptual problem about virtex
5......ok...i will try.....thank you everybody......

 

[Tricky]

i am using xilinx ISE 9 (VHDL) and modelslim........my program has
synthesized...but my problem is.. i did not understand..how to
implement it ..

i think.....still i have some conceptual problem about virtex
5......ok...i will try.....thank you everybody......

If you have the design in VHDL, then all you should need now is some
method of communication. I assume the FFT will consume a large volume
of data, so you probably need ethernet. There are probably some cores
available on the internet. You will have to connect the output of the
ethernet core to the input of your FFT and output from the FFT to the
ethernet. You will have to write some code on the PC side to control
the flow of data. There is a nice core called Quixtream from Tekmicro
that does gigabit ethernet on to an FPGA, but it's only supported on
Virtex2 and 2pros according to their website. It comes with all the
drivers to drive the PC side of things.

Otherwise, you might want to try and get hold of some "Hardware in the
loop" kind of kit. I know mathworks like to talk about it. They have a
small Xilinx board that slots into a PCMCIA slot and Simulink will tie
everything all together. Ive only seen a demo, so I dont know how
applicable it would be in this case.