How to run simulation in Xilinx 12.1 ISE

Discussion in 'VHDL' started by udayjayachandran, Jul 16, 2010.

  1. udayjayachandran

    udayjayachandran

    Joined:
    Jul 8, 2010
    Messages:
    6
    Hi,
    I have multiple seperate VHD files for a CPU. How can i run all the files and simulate the design to see the results. Can anyone help me. I have included all files by using add source option. But frm then i dont know how to proceed.



    -
    Thanks,
    UDAY
    udayjayachandran, Jul 16, 2010
    #1
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  2. udayjayachandran

    jeppe

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    Denmark
    Your multiple VHDL files must be used to form one large design - otherwise can't they be simulated together.

    Use structural VHDL or draw a Schematic with your component (VHDL files/modules)
    jeppe, Jul 16, 2010
    #2
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