Viswan said:
I am designing a hardware unit that can be used as an interface to a
sensor and the FPGA on which my rest of the hardware exists. I have
to generate some synchronizing clock signals at certain delays, to
start the communication.
for example 2 siignals are needed to be sent to sensor as follows.
data is bidirectional.
data <---> ----| |-------
|----------|
|-----| |----|
sclk <---- --| |----| |-----
I thought it would be better if I could generate it using delays..
ANother idea I have in my mind is to use counters and generate these
waveforms. But i doubt if there is any other good idea for this.
Hello,
I remember your post about the SHT7x, and thought this piece of code might
help you:
library ieee ;
use ieee.std_logic_1164.all ;
entity driver is
port (
rstb : in std_logic; -- Reset Active Low
clk : in std_logic; -- Clk Input
SCK : out std_logic; -- SCK
DATA : inout std_logic -- DATA
) ;
end driver ;
architecture rtl of driver is
begin
main : process (rstb, clk)
type state_t is (
idle,
start1,start2,start3,start4,start5,start6,
address1, --to be continued
ack1, --to be continued
waiting --to be continued
);
variable state : state_t;
begin
if rstb = '0' then
state := idle;
DATA <= 'Z';
SCK <= '0';
elsif clk'event and clk='1' then
case state is
when idle =>
state := start1;
when start1 =>
DATA <= '1';
SCK <= '1';
state := start2;
when start2 =>
DATA <= '0';
SCK <= '1';
state := start3;
when start3 =>
DATA <= '0';
SCK <= '0';
state := start4;
when start4 =>
DATA <= '0';
SCK <= '1';
state := start5;
when start5 =>
DATA <= '1';
SCK <= '1';
state := start6;
when start6 =>
DATA <= '1';
SCK <= '0';
state := address1;
when others =>
--to be continued
end case;
end if;
end process main;
If you need further help, contact me through e-mail, why is yours not working?
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