How to specify a package in Xilinx 8.1i

[Weng Tianxiang]

Hi,
I need your help.

I have 4 vhdl source files:
A-Package.vhd;
A1.vhd;
A2.vhd;
A3.vhd;

A-Package.vhd is a package defining all common functions and constants
used in all other modules.

If the 4 files are in the above order, Modelsim runs them without any
errors.

But with Xilinx 8.1i, errors happen.

The following is in more details.

In A1.vhd, it is a top module and there are generic definitions:
generic(
DATABITS : integer := DATA_BITS;
MODEBITS : integer := MODE_BITS;
);

A2.vhd and A3.vhd are components called by A1.vhd and have the same
generic definitions:
generic(
DATABITS : integer := DATA_BITS;
MODEBITS : integer := MODE_BITS;
);

I specify DATA_BITS/MODE_BITS in a global package A-Package.vhd.
constant DATA_BITS : integer := 6;
constant MODE_BITS : integer := 3;

In instantiations in A1, A2 and A3:
generic map(
DATABITS => DATA_BITS,
MODEBITS => MODE_BITS
)
port map(
....);

When running with ModelSim, there is no error, A-Package is first
compiled and DATA_BITS
and MODE_BITS are specified.

When running with Xilinx 8.1i, there are following warning and errors:
WARNING:Xst:616 - Invalid property "DATABITS 6": Did not attach to C0.
WARNING:Xst:616 - Invalid property "MODEBITS 3": Did not attach to C0.
WARNING:Xst:616 - Invalid property "DATABITS 6": Did not attach to C11.
WARNING:Xst:616 - Invalid property "MODEBITS 3": Did not attach to C11.
....
ERROR:NgdBuild:604 - logical block 'C0' with type 'ControlBlock_In_0C'
could not
be resolved. A pin name misspelling can cause this, a missing edif
or ngc
file, or the misspelling of a type name. Symbol 'ControlBlock_In_0C'
is not
supported in target 'acr2'.
ERROR:NgdBuild:604 - logical block 'C11' with type 'ControlBlock_In_0C'
could
not be resolved. A pin name misspelling can cause this, a missing
edif or ngc
file, or the misspelling of a type name. Symbol 'ControlBlock_In_0C'
is not
supported in target 'acr2'.

The problem is the ERROR MESSAGE DOESN'T CONTAIN THE MISSING OR
MISSPELLING PIN NAMES so that I cannot identify what pin is wrong.

I checked my instantiation code, and all pin names are matched. And
ModelSim
runs without errors.

Thank you.

Weng

 

[Weng Tianxiang]

Sorry. The problem is resolved.

The reason is that the project file doesn't contain the lower module
files while in its project file, lower level module names are shown.

Weng