S
savitha.john
I want to stop the simulation in between for VHDL.
Is there any construct similar to $finish( in verilog)
Is there any construct similar to $finish( in verilog)
I want to stop the simulation in between for VHDL.
Is there any construct similar to $finish( in verilog)
Thank you all.........I am using ncsim for simulation...and that too ,a
command line interface....
I have implemented an assertion failure as Mike said....That did
work...But still ..even I don't like seeing failure warnings
when the testbench passes.......
Thanks a lot Mike
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