How to stop simulation in VHDL?

Discussion in 'VHDL' started by savitha.john@gmail.com, Mar 24, 2006.

  1. Guest

    I want to stop the simulation in between for VHDL.
    Is there any construct similar to $finish( in verilog)
     
    , Mar 24, 2006
    #1
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  2. wrote:
    > I want to stop the simulation in between for VHDL.
    > Is there any construct similar to $finish( in verilog)


    Not exactly.
    Find "done_s" and "coda" in this page for
    an example of forcing all processes to wait:

    http://home.comcast.net/~mike_treseler/

    The other way is to force an assertion failure,
    but I don't like seeing failure warnings
    when the testbench passes.

    -- Mike Treseler
     
    Mike Treseler, Mar 24, 2006
    #2
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  3. When running ModelSim before loading project, clike menu: Simulate,
    click Runtime Option, set Default run time data you want: for example,
    200us, then click Apply

    After project is loaded, you must have known everything else to do.

    Each time you run your simulation, ModelSim will stop after the
    simulation time is finished.

    No coding is required.

    Weng
     
    Weng Tianxiang, Mar 25, 2006
    #3
  4. Guest

    Hi,
    u can use "break" commadn on vsim prmpt of the modelsim.
     
    , Mar 27, 2006
    #4
  5. Guest

    Hi,
    u can use "break" commadn on vsim prmpt of the modelsim.
     
    , Mar 27, 2006
    #5
  6. Guest

    Thank you all.........I am using ncsim for simulation...and that too ,a
    command line interface....
    I have implemented an assertion failure as Mike said....That did
    work...But still ..even I don't like seeing failure warnings
    when the testbench passes....... :) :)

    Thanks a lot Mike
     
    , Mar 27, 2006
    #6
  7. Guest

    wrote:
    > Thank you all.........I am using ncsim for simulation...and that too ,a
    > command line interface....
    > I have implemented an assertion failure as Mike said....That did
    > work...But still ..even I don't like seeing failure warnings
    > when the testbench passes....... :) :)
    >
    > Thanks a lot Mike


    I don't like seeing failure warnings either... :)

    I use the following syntax to end the simulation:
    assert false report "NONE. End of simulation." severity
    failure;

    The simulator then outputs the following:
    # ** Failure: NONE. End of simulation.

    Not a perfect solution but works for me...

    Pete
     
    , Mar 31, 2006
    #7
  8. jtw Guest

    A method I sometimes use is having all clocks 'automatically' stop
    (typically, sometime after a stimulus input file has finished); when there
    are no more processes pending, the simulation will stop.

    Alternatively, sometimes I call the simulation with a generic limiting the
    amount of time.

    JTW

    <> wrote in message
    news:...
    >
    > wrote:
    >> Thank you all.........I am using ncsim for simulation...and that too ,a
    >> command line interface....
    >> I have implemented an assertion failure as Mike said....That did
    >> work...But still ..even I don't like seeing failure warnings
    >> when the testbench passes....... :) :)
    >>
    >> Thanks a lot Mike

    >
    > I don't like seeing failure warnings either... :)
    >
    > I use the following syntax to end the simulation:
    > assert false report "NONE. End of simulation." severity
    > failure;
    >
    > The simulator then outputs the following:
    > # ** Failure: NONE. End of simulation.
    >
    > Not a perfect solution but works for me...
    >
    > Pete
    >
     
    jtw, Apr 1, 2006
    #8
  9. Hans Guest

    For those of you that are using Modelsim you can simple add a signal to your
    testbench and assert this signal at the end of the simulation. Then use the
    "when" statement in your script to stop the simulator.

    Example: stop Modelsim when the signal end_of_simulation='1'

    when -label end_of_simulation {end_of_sim == '1'} {echo "End of simulation"
    ; stop ;}

    # End of simulation
    # Simulation stop requested

    Let hope accellera will sort this out for SystemVHDL....HyperVHDL...or
    whatever they are planning to call it (assuming of course they are still
    actively working on it...)

    Hans
    www.ht-lab.com


    <> wrote in message
    news:...
    >I want to stop the simulation in between for VHDL.
    > Is there any construct similar to $finish( in verilog)
    >
     
    Hans, Apr 1, 2006
    #9
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