How To Synchronize FPGAs

Discussion in 'VHDL' started by Leroy Tanner, Sep 22, 2004.

  1. Leroy Tanner

    Leroy Tanner Guest

    Hello newsreaders,

    For a while I have been confronted with the following task which I find
    quite challenging but unfortuantely didn't manage to solve it, yet.
    What I want to do is to use 2-4 FPGAs (Xilinx Virtex 2 Pro) together on one
    printed circuit board (PCB). They are used to process a large amount of
    incoming serial data (data rates of several GHz's). My idea is to handle
    that data parallel by the 2-4 FPGAs. But now there arises the problem how to
    adequately split the data and how to synchronize the FPGAs among one
    another, in particular?
    Is it possible or first of all a realistic idea to synchronize multiple
    FPGAs in the GHz range? How can this be done without much protocoll
    overhead? I would like to do it without applying an extra transfer protocoll
    among the FPGAs just for that purpose! Up to this date I didn't find a
    proper solution, yet.
    Maybe someone can give me a hint? Any ideas how to solve that problem?

    Regards, Leroy Tanner
     
    Leroy Tanner, Sep 22, 2004
    #1
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  2. Leroy Tanner wrote:


    > What I want to do is to use 2-4 FPGAs (Xilinx Virtex 2 Pro) together on
    > one printed circuit board (PCB). They are used to process a large amount
    > of incoming serial data (data rates of several GHz's).


    What do you intend to do with all that data
    once you have it flowing into your fpga?

    > Maybe someone can give me a hint? Any ideas how to solve that problem?


    The problem of receiving GHz serial data includes.

    1. Converting the line levels to something you can deserialize.
    2. Creating a clock on your board that lines up with the received data.
    3. Deserializing the the line data to vectors at a more reasonable frequency
    4. Unstuff or decode the line data to find the packet boundaries.
    5. Process the data packets.

    Note that steps 1,2,3 may have to be done external to your fpga.

    -- Mike Treseler
     
    Mike Treseler, Sep 22, 2004
    #2
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  3. You can do it in structure of 2 levels of chips.

    First chip will receive all input data stream, then it divides the
    input data stream into 4 substreams by any algorithms and output them
    to 4 chips and let the 4 chips do any things.

    It is simple, reliable and achievable.

    Weng
     
    Weng Tianxiang, Sep 22, 2004
    #3
  4. Leroy Tanner

    Leroy Tanner Guest

    "Weng Tianxiang" <>:
    > You can do it in structure of 2 levels of chips.
    >
    > First chip will receive all input data stream, then it divides the
    > input data stream into 4 substreams by any algorithms and output them
    > to 4 chips and let the 4 chips do any things.


    Nevertheless I have to synchronize the 4 chips in the second level..!!
     
    Leroy Tanner, Sep 24, 2004
    #4
  5. Leroy Tanner

    Don Golding Guest

    Can you be more specific as to what the application is? This question is
    too broad ...

    Some thoughts:

    1) Obviously, all FPGA's are driven by a single clock.
    2) Assume you are using 4 FPGA's in parallel, create a 4 bit bus, one line
    for each FPGA, which allows all FPGA's to communicate with one another.
    This is basically a semaphore flag bus.
    3) Each FPGA has a single bi/directional pin which is set to '1' when the
    device is ready to process the next step in your algorithm or set to '0'
    when busy.
    4) When each process is completed within the individual FPGA's, the process
    waits for the semaphore bus to be all ones; '1111'.
    5) The reset routine initially sets semaphore flag to '0' then performs all
    of it's housekeeping tasks, then sets the semaphore to '1'. the next
    process waits until the semaphore bus ='1111'.

    I hope this helps,
    Don



    "Leroy Tanner" <> wrote in message
    news:cirg1i$j5q$-Berlin.DE...
    > Hello newsreaders,
    >
    > For a while I have been confronted with the following task which I find
    > quite challenging but unfortuantely didn't manage to solve it, yet.
    > What I want to do is to use 2-4 FPGAs (Xilinx Virtex 2 Pro) together on
    > one
    > printed circuit board (PCB). They are used to process a large amount of
    > incoming serial data (data rates of several GHz's). My idea is to handle
    > that data parallel by the 2-4 FPGAs. But now there arises the problem how
    > to
    > adequately split the data and how to synchronize the FPGAs among one
    > another, in particular?
    > Is it possible or first of all a realistic idea to synchronize multiple
    > FPGAs in the GHz range? How can this be done without much protocoll
    > overhead? I would like to do it without applying an extra transfer
    > protocoll
    > among the FPGAs just for that purpose! Up to this date I didn't find a
    > proper solution, yet.
    > Maybe someone can give me a hint? Any ideas how to solve that problem?
    >
    > Regards, Leroy Tanner
    >
    >
     
    Don Golding, Sep 24, 2004
    #5
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