How to use Block RAMs ??

[Asm4PIC]

i wrote this code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
--
ENTITY ram_asynch IS
GENERIC (d_width : natural := 8;
a_width : natural := 8);
PORT(data_in : IN unsigned(d_width-1 DOWNTO 0);
wr_en : IN std_logic;
address : IN unsigned(a_width-1 DOWNTO 0);
data_out : OUT unsigned(d_width-1 DOWNTO 0));
END ENTITY ram_asynch;
--
ARCHITECTURE Arch OF ram_asynch IS
SUBTYPE byte IS unsigned(d_width-1 DOWNTO 0);
TYPE mem_type IS ARRAY (natural RANGE <>) OF byte;
BEGIN
asynch : PROCESS(wr_en,data_in,address)
VARIABLE mem : mem_type(0 TO 2**a_width-1);
ATTRIBUTE ram_block : boolean;
ATTRIBUTE ram_block OF mem : VARIABLE IS TRUE;
BEGIN
IF (wr_en = '1') THEN
mem(to_integer(address)) := data_in;
END IF;
data_out <= mem(to_integer(address));
END PROCESS asynch;
END ARCHITECTURE Arch;

and the synthesis tool generates this report

# Resource Used Avail Utilization
# -----------------------------------------------
# IOs 25 86 29.07%
# Global Buffers 0 4 0.00%
# Function Generators 3143 384 818.49%
# CLB Slices 1572 192 818.75%
# Dffs or Latches 2048 672 304.76%
# Block RAMs 0 4 0.00%

How to force the synthesis tool to use Block RAMs instead of DFFs to
implement internal memory

thanx

 

[Andy]

i wrote this code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
--
ENTITY ram_asynch IS
GENERIC (d_width : natural := 8;
a_width : natural := 8);
PORT(data_in : IN unsigned(d_width-1 DOWNTO 0);
wr_en : IN std_logic;
address : IN unsigned(a_width-1 DOWNTO 0);
data_out : OUT unsigned(d_width-1 DOWNTO 0));
END ENTITY ram_asynch;
--
ARCHITECTURE Arch OF ram_asynch IS
SUBTYPE byte IS unsigned(d_width-1 DOWNTO 0);
TYPE mem_type IS ARRAY (natural RANGE <>) OF byte;
BEGIN
asynch : PROCESS(wr_en,data_in,address)
VARIABLE mem : mem_type(0 TO 2**a_width-1);
ATTRIBUTE ram_block : boolean;
ATTRIBUTE ram_block OF mem : VARIABLE IS TRUE;
BEGIN
IF (wr_en = '1') THEN
mem(to_integer(address)) := data_in;
END IF;
data_out <= mem(to_integer(address));
END PROCESS asynch;
END ARCHITECTURE Arch;

and the synthesis tool generates this report

# Resource Used Avail Utilization
# -----------------------------------------------
# IOs 25 86 29.07%
# Global Buffers 0 4 0.00%
# Function Generators 3143 384 818.49%
# CLB Slices 1572 192 818.75%
# Dffs or Latches 2048 672 304.76%
# Block RAMs 0 4 0.00%

How to force the synthesis tool to use Block RAMs instead of DFFs to
implement internal memory

thanx

Block rams are synchronous. You have to have a clock to use them.

Review your synthesis tool's documentation for synthesizable block ram
templates.

Also, for tests like this, you probably need to turn off IO
insertion.

Andy

 

[Asm4PIC]

Block rams are synchronous. You have to have a clock to use them.

Review your synthesis tool's documentation for synthesizable block ram
templates.

Also, for tests like this, you probably need to turn off IO
insertion.

Andy- Hide quoted text -

- Show quoted text -

thanx for advice

it works fine

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
--
ENTITY ram_synch IS
GENERIC (d_width : natural := 8;
a_width : natural := 8);
PORT(clock : IN std_logic;
data_in : IN unsigned(d_width-1 DOWNTO 0);
wr_en : IN std_logic;
address : IN unsigned(a_width-1 DOWNTO 0);
data_out : OUT unsigned(d_width-1 DOWNTO 0));
END ENTITY ram_synch;
--
ARCHITECTURE Arch OF ram_synch IS
SUBTYPE byte IS unsigned(d_width-1 DOWNTO 0);
TYPE mem_type IS ARRAY (natural RANGE <>) OF byte;
BEGIN
asynch : PROCESS(clock,wr_en,data_in,address)
VARIABLE mem : mem_type(0 TO 2**a_width-1);
BEGIN
IF rising_edge(clock) THEN
IF (wr_en = '1') THEN
mem(to_integer(address)) := data_in;
END IF;
data_out <= mem(to_integer(address));
END IF;
END PROCESS asynch;
END ARCHITECTURE Arch;

Ahmed Samieh

 

[Asm4PIC]

thanx for advice

it works fine

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
--
ENTITY ram_synch IS
GENERIC (d_width : natural := 8;
a_width : natural := 8);
PORT(clock : IN std_logic;
data_in : IN unsigned(d_width-1 DOWNTO 0);
wr_en : IN std_logic;
address : IN unsigned(a_width-1 DOWNTO 0);
data_out : OUT unsigned(d_width-1 DOWNTO 0));
END ENTITY ram_synch;
--
ARCHITECTURE Arch OF ram_synch IS
SUBTYPE byte IS unsigned(d_width-1 DOWNTO 0);
TYPE mem_type IS ARRAY (natural RANGE <>) OF byte;
BEGIN
asynch : PROCESS(clock,wr_en,data_in,address)
VARIABLE mem : mem_type(0 TO 2**a_width-1);
BEGIN
IF rising_edge(clock) THEN
IF (wr_en = '1') THEN
mem(to_integer(address)) := data_in;
END IF;
data_out <= mem(to_integer(address));
END IF;
END PROCESS asynch;
END ARCHITECTURE Arch;

Ahmed Samieh- Hide quoted text -

- Show quoted text -

Resource Used Avail Utilization
-----------------------------------------------
IOs 25 86 29.07%
Global Buffers 1 4 25.00%
Function Generators 0 384 0.00%
CLB Slices 0 192 0.00%
Dffs or Latches 0 672 0.00%
Block RAMs 1 4 25.00%