How to use expressions in named-association port map?

Discussion in 'VHDL' started by Alex Rast, Nov 9, 2004.

  1. Alex Rast

    Alex Rast Guest

    I'd like to use an expression in a port map using named association. None of
    the books or reference sources I've checked are clear on this problem. From
    what I see, it looks as though there is some way to do this, but there's no
    guidance on the syntax. Here's the situation I envision.

    I define a component that has a parametrised input bus (i.e. one of arbitrary
    width). Now, I want to use that component as part of a component that is itself
    parametrised. At some point, an upper-level instantiation sets a parameter that
    then sets the widths of the components lower in the hierarchy.

    So, let's say it goes something like this:

    entity someprimitivecomponent is
    generic (sub_bus_width : integer := somedefault);
    port (somebus : in std_logic_vector;
    someresult : out std_logic_vector);
    end someprimitivecomponent;

    entity someintermediatecomponent is
    generic (bus_width : integer := someotherdefault);
    port (anotherbus : in std_logic_vector;
    anotherresult : out std_logic_vector);
    end someintermediatecomponent;

    architecture parametrised of someintermediatecomponent is

    component someprimitivecomponent
    generic (sub_bus_width : integer := somedefault);
    port (somebus : in std_logic_vector;
    someresult : out std_logic_vector);
    end component;

    ... other declarations

    constant somenumber : integer := somevalue;
    constant someothernumber : integer := someothervalue;

    begin

    sub_component1 : someprimitivecomponent
    generic map (sub_bus_width := bus_width MOD somenumber)
    port map (somebus(((bus_width MOD somenumber)-1) downto 0) =>
    anotherbus(((bus_width MOD somenumber)-1) downto 0),
    someresult(((bus_width MOD someothernumber)-1) downto 0)
    => anotherresult(((bus_width MOD someothernumber)-1) downto 0));

    ... other instantiations and wiring

    end parametrised;

    entity sometopdesign is
    port (global_bus : in std_logic_vector(63 downto 0);
    output_bus : out std_logic_vector(31 downto 0));
    end sometopdesign;

    architecture 64Bit of sometopdesign is

    component someintermediatecomponent
    generic (bus_width : integer := someotherdefault);
    port (anotherbus : in std_logic_vector;
    anotherresult : out std_logic_vector);
    end component;

    ... other declarations

    begin

    component1 : someintermediatecomponent
    generic map (bus_width => 64)
    port map(anotherbus(63 downto 0) => global_bus(63 downto 0),
    anotherresult(31 downto 0) => output_bus(31 downto 0));


    ... other instantiations and wiring

    end 64Bit;

    However, the syntax checker chokes on this. It doesn't seem to want to accept
    the someprimitivecomponent instantiation in someintermediatecomponent, and
    seems to want to force the range of the formal ports in the instantiation to be
    a number. That is, if you have port map (somebus({expression} downto 0), the
    only things it seems to want to accept in {expression} are numbers, i.e.
    strings consisting only of the characters {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}. I
    certainly don't see anything in the literature available to me that leads me to
    believe this would have to be the case, and in fact it seems as though that
    would severely hamper the ability to use named association to describe slices
    of ports. What is the correct syntax, then, to achieve the result I need?

    --
    Alex Rast

    (remove d., .7, not, and .NOSPAM to reply)
     
    Alex Rast, Nov 9, 2004
    #1
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  2. Alex Rast

    Jim Lewis Guest

    Alex,
    There is a small syntax error in the instantiation, the fix
    is shown below, I don't know if it is also in your real design,
    but other than that, I don't see anything that sticks out
    at me. I have used generics and sig_nam'range when slicing
    objects. I have not used mod.

    Is this for a synthesis tool or simulator? Some synthesis tools
    may not like the components and entities not have constrained
    port sizes (even though the language allows it).

    > sub_component1 : someprimitivecomponent
    > generic map (sub_bus_width := bus_width MOD somenumber)


    -- Should be:
    generic map (sub_bus_width => bus_width MOD somenumber)


    > port map (somebus(((bus_width MOD somenumber)-1) downto 0) =>
    > anotherbus(((bus_width MOD somenumber)-1) downto 0),
    > someresult(((bus_width MOD someothernumber)-1) downto 0)
    > => anotherresult(((bus_width MOD someothernumber)-1) downto 0));
    >
    > ... other instantiations and wiring
    >
    > end parametrised;


    If you need more help, post something I can paste into a file
    and look at the errors.

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, Nov 10, 2004
    #2
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  3. Alex Rast

    Alex Rast Guest

    at Wed, 10 Nov 2004 00:14:07 GMT in <>,
    (Jim Lewis) wrote :

    >Alex,
    >There is a small syntax error in the instantiation, the fix
    >is shown below, ...
    >> sub_component1 : someprimitivecomponent
    >> generic map (sub_bus_width := bus_width MOD
    >> somenumber)

    >
    >-- Should be:
    > generic map (sub_bus_width => bus_width MOD
    > somenumber)


    Typo while typing in the post. In my VHDL code it's =>, not :=. So that
    wouldn't be the source of the problems.

    >Is this for a synthesis tool or simulator? Some synthesis tools
    >may not like the components and entities not have constrained
    >port sizes (even though the language allows it).


    Synthesis tool (Synplify). It's a recent version, so I'd imagine this
    wouldn't be the source of the problem (AFAIU, most of the strange
    synthesis-tool related constraints on parametrised code seem to apply
    mostly to older, legacy synthesis tools)

    --
    Alex Rast

    (remove d., .7, not, and .NOSPAM to reply)
     
    Alex Rast, Nov 10, 2004
    #3
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