How to use separate configuration file in the ISE project?

Discussion in 'VHDL' started by Rebecca, Jul 30, 2008.

  1. Rebecca

    Rebecca Guest

    I wrote a separate configuration file to tell which architecture
    should be used for the component declaration (u1, u2) in the top
    design. The configuration file is give as follow:

    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all;
    use IEEE.std_logic_arith.all;

    configuration cfg_entity_test of entity_test is
    for entity_test_arch
    for u1 : entity_u use entity work.entity_u(entity_u_arch_u1);
    end for;
    for u2 : entity_u use entity work.entity_u(entity_u_arch_u2);
    end for;
    end for;
    end cfg_entity_test;

    My question is how can I tell the ISE that this is the configuration
    for my top design “entity_test”? I added the configuration file to the
    project and it seemed that synthesis just ignored it.

    Thank you very much for kind help,
    Rebecca
     
    Rebecca, Jul 30, 2008
    #1
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  2. Rebecca wrote:

    > My question is how can I tell the ISE that this is the configuration
    > for my top design “entity_test”? I added the configuration file to the
    > project and it seemed that synthesis just ignored it.


    Last time I tried, ISE would not accept a vhdl configuration
    as a top entity. If this is still true, we are stuck
    with using a file list instead.

    -- Mike Treseler
     
    Mike Treseler, Jul 30, 2008
    #2
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  3. Rebecca

    Rebecca Guest

    On Jul 30, 6:50 pm, Mike Treseler <> wrote:
    > Rebecca wrote:
    > > My question is how can I tell the ISE that this is the configuration
    > > for my top design “entity_test”? I added the configuration file to the
    > > project and it seemed that synthesis just ignored it.

    >
    > Last time I tried, ISE would not accept a vhdl configuration
    > as a top entity. If this is still true, we are stuck
    > with using a file list instead.
    >
    >        -- Mike Treseler


    Can we use the configuration file for non-top design files in ISE?
    And would you please tell me how to using a file list?
    Thanks a lot,

    Rebecca
     
    Rebecca, Jul 31, 2008
    #3
  4. Rebecca wrote:

    > Can we use the configuration file for non-top design files in ISE?

    I doubt it. Try it and see:
    http://www.xilinx.com/ise/logic_design_prod/webpack.htm

    > And would you please tell me how to using a file list?

    To cover verilog, synthesis accepts a top module/entity
    name (ports=device pins) and a list of the hdl files
    that represent the top, and the module/entity instances
    that fill in the design.
    Start with the new project "wizard". Good luck.

    -- Mike Treseler
     
    Mike Treseler, Jul 31, 2008
    #4
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