How to use SRAM Vhdl with DE2 Board??

Discussion in 'VHDL' started by Little34, Apr 15, 2010.

  1. Little34

    Little34

    Joined:
    Apr 15, 2010
    Messages:
    1
    I have a project in which i have to write binary data to the SRAM and then later read that data from the SRAM and display it to a seven segment display. However this is hard to due since i don't understand how to send/read the data to the SRAM in the first place.

    can anyone explain how to write/read data to an SRAM chip in VHDL using the Altera DE2 board with cyclone II chip???
     
    Little34, Apr 15, 2010
    #1
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  2. Little34

    robin244

    Joined:
    Jan 22, 2011
    Messages:
    1
    SRAM access

    Hello,
    I know it is late, but this code works:

    Note: SW(17) and SW(16) are used to set the address, SW(15) is write enable, SW(7) down to SW(0) are data inputs and LEDR(7) down to LEDR(0) are used to display the memory content of the selected address.

    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    
    entity top_level_entity is
    	port(
    		SW: in std_logic_vector(17 downto 0);
    		LEDR: out std_logic_vector(17 downto 0);
    		
    		SRAM_ADDR: out std_logic_vector(19 downto 0);
    		SRAM_DQ: inout std_logic_vector(15 downto 0);
    		SRAM_CE_N: out std_logic;
    		SRAM_OE_N: out std_logic;
    		SRAM_WE_N: out std_logic;
    		SRAM_UB_N: out std_logic;
    		SRAM_LB_N: out std_logic
    	);
    end top_level_entity;
    
    
    architecture inside_top_level_entity of top_level_entity is
    
    	signal address: std_logic_vector(1 downto 0);
    	signal data: std_logic_vector(7 downto 0);
    	signal output: std_logic_vector(7 downto 0);
    	signal we: std_logic;
    	
    begin
    
    	address <= SW(17 downto 16);
    	data <= SW(7 downto 0) when SW(15) = '1' else (others => 'Z');
    	LEDR(7 downto 0) <= output;
    
    	SRAM_WE_N <= not SW(15);
    	
    	SRAM_CE_N <= '0';
    	SRAM_OE_N <= '0';
    	SRAM_UB_N <= '0';
    	SRAM_LB_N <= '0';
    	
    	SRAM_ADDR(19 downto 2) <= (others => '0');
    	SRAM_ADDR(1 downto 0) <= address;
    	
    	SRAM_DQ(15 downto 8) <= (others => '0');
    	SRAM_DQ(7 downto 0) <= data;
    	
    	output <= SRAM_DQ(7 downto 0);
    
    end inside_top_level_entity;
     
    Last edited: Jan 22, 2011
    robin244, Jan 22, 2011
    #2
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