how to use "wait" or dealy in a process?

A

Amit

Hello group,

I need to simulate a dealy in a process. However I'm getting an error
as "A wait statement is illegal for a process with a sensitivity
list."

What should I do?

Regards.
 
A

Amit

Hello group,

I need to simulate a dealy in a process. However I'm getting an error
as "A wait statement is illegal for a process with a sensitivity
list."

What should I do?

Regards.


Of course, I am having a sensitive list in my process since I'm using
FSM states. What I'm trying to do is creating a delay. Is it possible?

Thanks.
 
J

JK

Of course, I am having a sensitive list in my process since I'm using
FSM states. What I'm trying to do is creating a delay. Is it possible?

Thanks.

op <= ip after 10 ns;
 
J

JK

op <= ip after 10 ns;- Hide quoted text -

This is for simulation purpose... It cant be synthesized.
Synthesizers ignore delay expressions('after'....)

Regards,
JK
 
A

Amit

This is for simulation purpose... It cant be synthesized.
Synthesizers ignore delay expressions('after'....)

Regards,
JK


JK,

Thanks indeed for your help.
 
P

Pieter Hulshoff

Amit said:
I need to simulate a dealy in a process. However I'm getting an error
as "A wait statement is illegal for a process with a sensitivity
list."

A sensitive list is already considered a complete wait statement in itself, so
the VHDL language does not allow another wait statement. Remove your sensitivity
list, and add a WAIT ON <previous sensitivity list>; statement to the top of
your process.

Regards,

Pieter Hulshoff
 

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