how to use "wait" or dealy in a process?

Discussion in 'VHDL' started by Amit, Jun 9, 2007.

  1. Amit

    Amit Guest

    Hello group,

    I need to simulate a dealy in a process. However I'm getting an error
    as "A wait statement is illegal for a process with a sensitivity
    list."

    What should I do?

    Regards.
     
    Amit, Jun 9, 2007
    #1
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  2. Amit

    Amit Guest

    On Jun 8, 10:03 pm, Amit <> wrote:
    > Hello group,
    >
    > I need to simulate a dealy in a process. However I'm getting an error
    > as "A wait statement is illegal for a process with a sensitivity
    > list."
    >
    > What should I do?
    >
    > Regards.



    Of course, I am having a sensitive list in my process since I'm using
    FSM states. What I'm trying to do is creating a delay. Is it possible?

    Thanks.
     
    Amit, Jun 9, 2007
    #2
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  3. Amit

    JK Guest

    On Jun 9, 10:10 am, Amit <> wrote:
    > On Jun 8, 10:03 pm, Amit <> wrote:
    >
    > > Hello group,

    >
    > > I need to simulate a dealy in a process. However I'm getting an error
    > > as "A wait statement is illegal for a process with a sensitivity
    > > list."

    >
    > > What should I do?

    >
    > > Regards.

    >
    > Of course, I am having a sensitive list in my process since I'm using
    > FSM states. What I'm trying to do is creating a delay. Is it possible?
    >
    > Thanks.


    op <= ip after 10 ns;
     
    JK, Jun 9, 2007
    #3
  4. Amit

    JK Guest

    On Jun 9, 9:50 pm, JK <> wrote:
    > op <= ip after 10 ns;- Hide quoted text -


    This is for simulation purpose... It cant be synthesized.
    Synthesizers ignore delay expressions('after'....)

    Regards,
    JK
     
    JK, Jun 9, 2007
    #4
  5. Amit

    Amit Guest

    On Jun 9, 11:18 am, JK <> wrote:
    > On Jun 9, 9:50 pm, JK <> wrote:
    >
    > > op <= ip after 10 ns;- Hide quoted text -

    >
    > This is for simulation purpose... It cant be synthesized.
    > Synthesizers ignore delay expressions('after'....)
    >
    > Regards,
    > JK



    JK,

    Thanks indeed for your help.
     
    Amit, Jun 9, 2007
    #5
  6. Amit wrote:
    > I need to simulate a dealy in a process. However I'm getting an error
    > as "A wait statement is illegal for a process with a sensitivity
    > list."


    A sensitive list is already considered a complete wait statement in itself, so
    the VHDL language does not allow another wait statement. Remove your sensitivity
    list, and add a WAIT ON <previous sensitivity list>; statement to the top of
    your process.

    Regards,

    Pieter Hulshoff
     
    Pieter Hulshoff, Jun 11, 2007
    #6
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