How to write a testbench

Discussion in 'VHDL' started by ZHIQUAN, Apr 23, 2007.

  1. ZHIQUAN

    ZHIQUAN Guest

    I want to know how to write a testbench for a program with IP core
    BlockRam.
    My main program is like that:

    entity DCDcore is
    port (
    DCDCLK : in std_logic;
    RESET : in std_logic;
    IPTADDRB : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); -- address for
    reading ram_input port b
    IPTDOUTB : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- data from
    ram_input prot b
    RETADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- address for
    reading result vector h, connect to ram_h port a
    RETDOUTR : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- data output
    from ram_h port a (the result vector h)
    STDCD : in std_logic; -- start dcd computing triggle signal,
    from application component
    DCDOVER: out std_logic -- dcd finished triggle signal to
    application component
    );
    end DCDcore;
    architecture Behavioral of DCDcore is
    -------theta ram signal declaration------------------------
    component theta_ram
    port(
    clka : in std_logic;
    addra: in std_logic_vector(6 downto 0);
    dina : in std_logic_vector(31 downto 0);
    wea : in std_logic;
    --
    clkb : in std_logic;
    addrb: in std_logic_vector(6 downto 0);
    doutb: out std_logic_vector(31 downto 0)
    );
    end component;
    signal thtaddra, thtaddrb : std_logic_vector(6 downto 0);
    signal thtdina, thtdoutb: std_logic_vector(31 downto 0);
    signal thtwea: std_logic;
    ------------------- h ram signal declaration-------------------
    component h_ram
    port( clka : in std_logic;
    addra: in std_logic_vector(7 downto 0);
    douta: out std_logic_vector(7 downto 0); ---port a: read only
    ---
    clkb : in std_logic;
    addrb: in std_logic_vector(6 downto 0); --port b: read and write
    dinb: in std_logic_vector(15 downto 0);
    doutb: out std_logic_vector(15 downto 0);
    web: in std_logic
    );
    end component;
    ..................................[Declare some necessary signal
    type]----------------

    begin
    vector_theta_ram_inst:theta_ram port map
    (
    clka => DCDCLK,
    ADDRA=> thtaddra,
    DINA=> thtdina,
    wea =>thtwea,
    ---
    clkb=>dcdclk,
    addrb=>thtaddrb,
    doutb=>thtdoutb
    );
    vector_h_ram_inst:h_ram port map
    (
    clka=>dcdclk,
    addra=>retaddr, --address from wrlogic
    douta=>retdoutr, --data out to the uart
    clkb=>dcdclk,
    addrb=>haddrb,
    dinb=>hdinb,
    doutb=>hdoutb,
    web=>hweb
    );

    The theta_ram and h_ram are BlockRAM from IP core generator. H-ram is
    stored the final result and sent back to Matlab.

    I want to simulate the Algorithm without the transmission part. I
    run the test bech of ISE7.1 It generated a template for the testbench
    automatically. I need to write all data with the 'IN' type by
    myself. I surely can write the input data for caculation. But how can
    I write '' RETADDR'' which connects with h_ram. It is not such a easy
    job just writing a data and the address for every clock. I have no
    more experience on writing testbench. Just have written very simple
    example before. Could you tell me how to write such a complex program?
    Thanks a lot.
     
    ZHIQUAN, Apr 23, 2007
    #1
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  2. ZHIQUAN wrote:
    > I want to know how to write a testbench for a program with IP core
    > BlockRam.
    > It is not such a easy
    > job just writing a data and the address for every clock.


    I use procedures to handle complexity.
    See the reference testbench here:
    http://home.comcast.net/~mike_treseler/
    for an example.

    -- Mike Treseler
     
    Mike Treseler, Apr 23, 2007
    #2
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  3. ZHIQUAN

    ZHIQUAN Guest

    Thanks Mike.
    Mike Treseler wrote:
    > ZHIQUAN wrote:
    > > I want to know how to write a testbench for a program with IP core
    > > BlockRam.
    > > It is not such a easy
    > > job just writing a data and the address for every clock.

    >
    > I use procedures to handle complexity.
    > See the reference testbench here:
    > http://home.comcast.net/~mike_treseler/
    > for an example.
    >
    > -- Mike Treseler
     
    ZHIQUAN, Apr 23, 2007
    #3
  4. ZHIQUAN wrote:

    > Can I ask a question about statement of 'report' and 'assert' thing.
    > I saw you use the statement sometimes. I found them in vhdl book that
    > 'report' is an output msg. I want to know how to use these commands.


    http://www.nt-nv.fh-koeln.de/Labor/VhdlEnglish/Kap5/k54.html#Ass

    > Where do these output go?


    To standard output -- usually the simulator command line.

    > Where I can find the information content
    > quoted in the 'report'. They will really output or just like a
    > comment. Thanks.


    The report string is printed to the simulator
    window or terminal. I can't run a testbench
    without a simulator.

    -- Mike Treseler
     
    Mike Treseler, Apr 24, 2007
    #4
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