How to write a VHDL code for 1Hz signal?

Discussion in 'VHDL' started by Vagant, Jan 8, 2008.

  1. Vagant

    Vagant Guest

    Hello,

    I am a newbie to VHDL programming and want to test my FPGA board with
    a code which lights a LED every second. To do this I need a VHDL code
    for 1 Hz signal generator. Unfortunately, I cannot find such in Web.
    Also I am not experienced in VHDL programming and not sure how to
    write such a code. If you have any similar code could you put it in
    this thread, please or give me some idea how to write this. I also
    wonder - is it necessary to use a clock for such signal generator?
    Vagant, Jan 8, 2008
    #1
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  2. Vagant schrieb:

    > I am a newbie to VHDL programming and want to test my FPGA board with
    > a code which lights a LED every second. To do this I need a VHDL code
    > for 1 Hz signal generator. Unfortunately, I cannot find such in Web.


    Take your clock (which is running at X MHz) and divide it by X.


    process(reset_n,clk)
    variable cnt : integer;
    begin
    if (reset_n='0') then
    clk_out<='0';
    cnt:=0;
    elsif rising_edge(clk) then
    if (cnt=divider_half-1) then
    clk_out<=NOT(clk_out);
    cnt:=0;
    else
    cnt:=cnt+1;
    end if;
    end if;
    end process;

    Note that divider_half is X/2.

    The code is not tested - just written in the mail program.

    Ralf
    Ralf Hildebrandt, Jan 8, 2008
    #2
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  3. Vagant

    Vagant Guest

    On Jan 8, 10:22 pm, Ralf Hildebrandt <> wrote:
    > Vagant schrieb:
    >
    > > I am a newbie to VHDL programming and want to test my FPGA board with
    > > a code which lights a LED every second. To do this I need a VHDL code
    > > for 1 Hz signal generator. Unfortunately, I cannot find such in Web.

    >
    > Take your clock (which is running at X MHz) and divide it by X.
    >
    > process(reset_n,clk)
    > variable   cnt   : integer;
    > begin
    > if (reset_n='0') then
    >         clk_out<='0';
    >         cnt:=0;
    > elsif rising_edge(clk) then
    >         if (cnt=divider_half-1) then
    >                 clk_out<=NOT(clk_out);
    >                 cnt:=0;
    >         else
    >                 cnt:=cnt+1;
    >         end if;
    > end if;
    > end process;
    >
    > Note that divider_half is X/2.
    >
    > The code is not tested - just written in the mail program.
    >
    > Ralf


    Thank you. I just wonder where I could get a complete listing (which
    includes 'entity' part)?
    Vagant, Jan 8, 2008
    #3
  4. Vagant wrote:

    > Thank you. I just wonder where I could get a complete listing (which
    > includes 'entity' part)?


    Do you have a text editor?
    Didn't the board come with some examples?

    Here's a related example including an entity:
    http://home.comcast.net/~mike_treseler/count_enable.vhd

    -- Mike Treseler
    Mike Treseler, Jan 8, 2008
    #4
  5. Vagant

    Vagant Guest

    On Jan 8, 10:22 pm, Ralf Hildebrandt <> wrote:
    >
    > Take your clock (which is running at X MHz) and divide it by X.
    >

    I guess it should be divided by X*10^6 to get 1 Hz, isn't it?
    Vagant, Jan 8, 2008
    #5
  6. Vagant

    Vagant Guest

    On Jan 8, 11:12 pm, Mike Treseler <> wrote:
    > Vagant wrote:
    > > Thank you. I just wonder where I could get a complete listing (which
    > > includes 'entity' part)?

    >
    > Do you have a text editor?
    > Didn't the board come with some examples?
    >
    > Here's a related example including an entity:http://home.comcast.net/~mike_treseler/count_enable.vhd
    >
    >         -- Mike Treseler


    No, it's not what I am asking about.
    Vagant, Jan 9, 2008
    #6
  7. Vagant

    Vagant Guest

    On Jan 8, 10:22 pm, Ralf Hildebrandt <> wrote:
    > Vagant schrieb:
    >
    > > I am a newbie to VHDL programming and want to test my FPGA board with
    > > a code which lights a LED every second. To do this I need a VHDL code
    > > for 1 Hz signal generator. Unfortunately, I cannot find such in Web.

    >
    > Take your clock (which is running at X MHz) and divide it by X.
    >
    > process(reset_n,clk)
    > variable   cnt   : integer;
    > begin
    > if (reset_n='0') then
    >         clk_out<='0';
    >         cnt:=0;
    > elsif rising_edge(clk) then
    >         if (cnt=divider_half-1) then
    >                 clk_out<=NOT(clk_out);
    >                 cnt:=0;
    >         else
    >                 cnt:=cnt+1;
    >         end if;
    > end if;
    > end process;
    >
    > Note that divider_half is X/2.
    >
    > The code is not tested - just written in the mail program.
    >
    > Ralf


    However the syntax check gives an error message:

    Parameter clk_out of mode out can not be associated with a formal
    parameter of mode in.

    for the line:
    clk_out<=NOT(clk_out);
    Vagant, Jan 9, 2008
    #7
  8. Vagant

    Guest

    On Jan 9, 2:57 am, Vagant <> wrote:
    > On Jan 8, 10:22 pm, Ralf Hildebrandt <> wrote:
    >
    > > Take your clock (which is running at X MHz) and divide it by X.

    >
    > I guess it should be divided by X*10^6 to get 1 Hz, isn't it?


    Not really. You're already using your clk to increment cnt. You just
    need to divide it by X.

    For instance, if you had a clock running at 50 MHz, cnt would
    increment 50,000 times a second. Divide it by 50 and you're left with
    a cnt that increments a thousand times a second - a 1 MHz clock.
    , Jan 9, 2008
    #8
  9. Vagant

    Vagant Guest

    On Jan 9, 8:23 am, wrote:
    > On Jan 9, 2:57 am, Vagant <> wrote:
    >
    > > On Jan 8, 10:22 pm, Ralf Hildebrandt <> wrote:

    >
    > > > Take your clock (which is running at X MHz) and divide it by X.

    >
    > > I guess it should be divided by X*10^6 to get 1 Hz, isn't it?

    >
    > Not really. You're already using your clk to increment cnt. You just
    > need to divide it by X.
    >
    > For instance, if you had a clock running at 50 MHz, cnt would
    > increment 50,000 times a second. Divide it by 50 and you're left with
    > a cnt that increments a thousand times a second - a 1 MHz clock.


    Well, but I need 1 Hz clock not 1 MHz.
    Vagant, Jan 9, 2008
    #9
  10. Vagant

    Guest

    On Jan 9, 11:23 am, Vagant <> wrote:
    > On Jan 8, 10:22 pm, Ralf Hildebrandt <> wrote:
    >
    >
    >
    >
    >
    > > Vagant schrieb:

    >
    > > > I am a newbie to VHDL programming and want to test my FPGA board with
    > > > a code which lights a LED every second. To do this I need a VHDL code
    > > > for 1 Hz signal generator. Unfortunately, I cannot find such in Web.

    >
    > > Take your clock (which is running at X MHz) and divide it by X.

    >
    > > process(reset_n,clk)
    > > variable   cnt   : integer;
    > > begin
    > > if (reset_n='0') then
    > >         clk_out<='0';
    > >         cnt:=0;
    > > elsif rising_edge(clk) then
    > >         if (cnt=divider_half-1) then
    > >                 clk_out<=NOT(clk_out);
    > >                 cnt:=0;
    > >         else
    > >                 cnt:=cnt+1;
    > >         end if;
    > > end if;
    > > end process;

    >
    > > Note that divider_half is X/2.

    >
    > > The code is not tested - just written in the mail program.

    >
    > > Ralf

    >
    > However the syntax check gives an error message:
    >
    > Parameter clk_out of mode out can not be associated with a formal
    > parameter of mode in.
    >
    > for the line:
    > clk_out<=NOT(clk_out);- Hide quoted text -
    >
    > - Show quoted text -


    You can not have a port of mode "out" being assigned to another
    signal. That makes sense if you think in terms of hardware, doesn't
    it? :)

    I can give you two solutions:
    1. Change the mode of clk_out to "inout."
    2. A better solution would be to declare an internal signal and assign
    it to clk_out after the process. For example,

    signal clk_sig : std_logic;
    process(reset_n,clk)
    variable cnt : integer;
    begin
    if (reset_n='0') then
    clk_sig<='0';
    cnt:=0;
    elsif rising_edge(clk) then
    if (cnt=divider_half-1) then
    clk_sig<=NOT(clk_sig);
    cnt:=0;
    else
    cnt:=cnt+1;
    end if;
    end if;
    end process;

    clk_out <= clk_sig;
    , Jan 9, 2008
    #10
  11. Vagant

    Guest

    On Jan 9, 11:25 am, Vagant <> wrote:
    > On Jan 9, 8:23 am, wrote:
    >
    > > On Jan 9, 2:57 am, Vagant <> wrote:

    >
    > > > On Jan 8, 10:22 pm, Ralf Hildebrandt <> wrote:

    >
    > > > > Take your clock (which is running at X MHz) and divide it by X.

    >
    > > > I guess it should be divided by X*10^6 to get 1 Hz, isn't it?

    >
    > > Not really. You're already using your clk to increment cnt. You just
    > > need to divide it by X.

    >
    > > For instance, if you had a clock running at 50 MHz, cnt would
    > > increment 50,000 times a second. Divide it by 50 and you're left with
    > > a cnt that increments a thousand times a second - a 1 MHz clock.

    >
    > Well, but I need 1 Hz clock not 1 MHz.


    Whoops, my mistake. The line should have been:
    Divide it by 50 and you're left with
    a cnt that increments a thousand times a second - a 1 Hz clock.

    Sorry.
    , Jan 9, 2008
    #11
  12. Vagant

    Guest

    On Jan 9, 11:30 am, wrote:
    > On Jan 9, 11:25 am, Vagant <> wrote:
    >
    >
    >
    >
    >
    > > On Jan 9, 8:23 am, wrote:

    >
    > > > On Jan 9, 2:57 am, Vagant <> wrote:

    >
    > > > > On Jan 8, 10:22 pm, Ralf Hildebrandt <> wrote:

    >
    > > > > > Take your clock (which is running at X MHz) and divide it by X.

    >
    > > > > I guess it should be divided by X*10^6 to get 1 Hz, isn't it?

    >
    > > > Not really. You're already using your clk to increment cnt. You just
    > > > need to divide it by X.

    >
    > > > For instance, if you had a clock running at 50 MHz, cnt would
    > > > increment 50,000 times a second. Divide it by 50 and you're left with
    > > > a cnt that increments a thousand times a second - a 1 MHz clock.

    >
    > > Well, but I need 1 Hz clock not 1 MHz.

    >
    > Whoops, my mistake. The line should have been:
    > Divide it by 50 and you're left with
    > a cnt that increments a thousand times a second - a 1 Hz clock.
    >
    > Sorry.- Hide quoted text -
    >
    > - Show quoted text -


    No, on second thought, you're right. For a 50 MHz clock, you would
    count to 24999 before toggling clk_out.
    , Jan 9, 2008
    #12
  13. Vagant

    Vagant Guest

    On Jan 9, 8:32 am, wrote:
    > On Jan 9, 11:30 am, wrote:
    >
    >
    >
    >
    >
    > > On Jan 9, 11:25 am, Vagant <> wrote:

    >
    > > > On Jan 9, 8:23 am, wrote:

    >
    > > > > On Jan 9, 2:57 am, Vagant <> wrote:

    >
    > > > > > On Jan 8, 10:22 pm, Ralf Hildebrandt <> wrote:

    >
    > > > > > > Take your clock (which is running at X MHz) and divide it by X.

    >
    > > > > > I guess it should be divided by X*10^6 to get 1 Hz, isn't it?

    >
    > > > > Not really. You're already using your clk to increment cnt. You just
    > > > > need to divide it by X.

    >
    > > > > For instance, if you had a clock running at 50 MHz, cnt would
    > > > > increment 50,000 times a second. Divide it by 50 and you're left with
    > > > > a cnt that increments a thousand times a second - a 1 MHz clock.

    >
    > > > Well, but I need 1 Hz clock not 1 MHz.

    >
    > > Whoops, my mistake. The line should have been:
    > > Divide it by 50 and you're left with
    > > a cnt that increments a thousand times a second - a 1 Hz clock.

    >
    > > Sorry.- Hide quoted text -

    >
    > > - Show quoted text -

    >
    > No, on second thought, you're right. For a 50 MHz clock, you would
    > count to 24999 before toggling clk_out.- Hide quoted text -
    >
    > - Show quoted text -


    Thank you. I have corrected the code and now it looks like this (is
    this correct?):

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity sig_gen is
    Port (clk : in STD_LOGIC;
    reset_n : in STD_LOGIC;
    clk_out : out STD_LOGIC);
    end entity sig_gen;

    architecture Behavioral of sig_gen is
    signal clk_sig : std_logic;
    begin
    process(reset_n,clk)
    variable cnt : integer;
    begin
    if (reset_n='0') then
    clk_sig<='0';
    cnt:=0;
    elsif rising_edge(clk) then
    if (cnt=2499-1) then
    clk_sig<=NOT(clk_sig);
    cnt:=0;
    else
    cnt:=cnt+1;
    end if;
    end if;
    end process;

    clk_out <= clk_sig;

    end Behavioral;
    Vagant, Jan 9, 2008
    #13
  14. On Jan 9, 3:43 pm, Vagant <> wrote:
    > On Jan 9, 8:32 am, wrote:
    >
    >
    >
    > > On Jan 9, 11:30 am, wrote:

    >
    > > > On Jan 9, 11:25 am, Vagant <> wrote:

    >
    > > > > On Jan 9, 8:23 am, wrote:

    >
    > > > > > On Jan 9, 2:57 am, Vagant <> wrote:

    >
    > > > > > > On Jan 8, 10:22 pm, Ralf Hildebrandt <> wrote:

    >
    > > > > > > > Take your clock (which is running at X MHz) and divide it by X.

    >
    > > > > > > I guess it should be divided by X*10^6 to get 1 Hz, isn't it?

    >
    > > > > > Not really. You're already using your clk to increment cnt. You just
    > > > > > need to divide it by X.

    >
    > > > > > For instance, if you had a clock running at 50 MHz, cnt would
    > > > > > increment 50,000 times a second. Divide it by 50 and you're left with
    > > > > > a cnt that increments a thousand times a second - a 1 MHz clock.

    >
    > > > > Well, but I need 1 Hz clock not 1 MHz.

    >
    > > > Whoops, my mistake. The line should have been:
    > > > Divide it by 50 and you're left with
    > > > a cnt that increments a thousand times a second - a 1 Hz clock.

    >
    > > > Sorry.- Hide quoted text -

    >
    > > > - Show quoted text -

    >
    > > No, on second thought, you're right. For a 50 MHz clock, you would
    > > count to 24999 before toggling clk_out.- Hide quoted text -

    >
    > > - Show quoted text -

    >
    > Thank you. I have corrected the code and now it looks like this (is
    > this correct?):
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    >
    > entity sig_gen is
    > Port (clk : in STD_LOGIC;
    > reset_n : in STD_LOGIC;
    > clk_out : out STD_LOGIC);
    > end entity sig_gen;
    >
    > architecture Behavioral of sig_gen is
    > signal clk_sig : std_logic;
    > begin
    > process(reset_n,clk)
    > variable cnt : integer;
    > begin
    > if (reset_n='0') then
    > clk_sig<='0';
    > cnt:=0;
    > elsif rising_edge(clk) then
    > if (cnt=2499-1) then
    > clk_sig<=NOT(clk_sig);
    > cnt:=0;
    > else
    > cnt:=cnt+1;
    > end if;
    > end if;
    > end process;
    >
    > clk_out <= clk_sig;
    >
    > end Behavioral;



    Have you checked that your board provides you with a 50 MHz clock? I
    quoted 50 just as an example. :)
    If yes, then you should count from 0 to 24999 (i.e., 25000 50 MHz
    clocks or half a second) and toggle clk_sig. Then you reset the count
    to 0 and start again. At the end of the next 25000 50 MHz clocks (or
    another half a second) you toggle clk_sig again and so on.

    So, your code should be:
    > if (cnt=25000-1) then


    Of course, (25000 - 1) is 24999. So you could also write:
    > if (cnt=24999) then


    I hope the calculation is clear. To give another example, for a 10 MHz
    clock, you count from 0 to 4999 (5000 10 MHz clocks).

    While coding, you could also declare the count limit as a constant.

    constant HALF_FREQ : INTEGER := 25000;

    So,
    > if (cnt=HALF_FREQ-1) then


    That way, if you decided to change the clock later on, you would only
    have to change the constant at one place. This could be helpful if you
    write a really large piece of code.
    Ponceludon de Malavoy, Jan 9, 2008
    #14
  15. Vagant a écrit :
    > On Jan 8, 11:12 pm, Mike Treseler <> wrote:
    >> Vagant wrote:
    >>> Thank you. I just wonder where I could get a complete listing (which
    >>> includes 'entity' part)?

    >> Do you have a text editor?
    >> Didn't the board come with some examples?
    >>
    >> Here's a related example including an entity:http://home.comcast.net/~mike_treseler/count_enable.vhd
    >>
    >> -- Mike Treseler

    >
    > No, it's not what I am asking about.


    The response of Mike, if I understood it rightly, means that a so simple
    question can be answered by yourself if you take the time to read the notice of
    your board, or if any of a VHDL book for beginner.

    Do not expect the forum's guys to do your project at your place : it will not
    learn you anything.

    That I read below let me out of mind...

    50Mhz is 50 000 000 period per second. So you have to divide it by 50 000 000 go
    get 1Hz, or to count two times from 0 to 24 999 999.
    I hope the error was to see if someone follows ?
    :)

    Pascal
    Pascal Peyremorte, Jan 9, 2008
    #15
  16. Vagant

    Vagant Guest

    On Jan 9, 4:14 pm, Pascal Peyremorte
    <> wrote:
    >
    > The response of Mike, if I understood it rightly, means that a so simple
    > question can be answered by yourself if you take the time to read the notice of
    > your board, or if any of a VHDL book for beginner.
    >
    > Do not expect the forum's guys to do your project at your place : it will not
    > learn you anything.
    >
    >
    > Pascal


    Well, a reply with a long code which was not asked would not be
    helpful either and if one does not like question then just reply
    nothing.
    Vagant, Jan 9, 2008
    #16
  17. Vagant

    Guest

    >Well, a reply with a long code which was not asked would not be
    >helpful either and if one does not like question then just reply
    >nothing.


    As I understand it, you have a PhD in nuclear magnetic resonance
    (Manchester 2004), so FPGAs and the associated HDLs are not beyond
    your abilities.

    But, as I said earlier, you need to learn some basic electronics and
    logic before you can handle these more recent developments, because
    most of those working with HDLs have that experience of older
    technologies and what you read will almost always assume that.

    Did you think it was going to be easy?

    Mike
    , Jan 9, 2008
    #17
  18. Vagant

    Guest

    >Well, a reply with a long code which was not asked would not be
    >helpful either and if one does not like question then just reply
    >nothing.


    off-topic : Esli Vy esche v Manchestere, u nas vecherinka russkaya v
    gorode Bolton v subotu (12.01.2008) ot 18:00 na pabe "Balmoral" (v
    tsentre). Stoit vsego 60 funtov, tak, esli pridut N chelovek, prosyat
    c kazhdogo 60/N funtov. Mike
    , Jan 9, 2008
    #18
  19. Vagant

    Vagant Guest

    On Jan 9, 4:56 pm, wrote:
    > >Well, a reply with a long code which was not asked would not be
    > >helpful either and if one does not like question then just reply
    > >nothing.

    >
    > off-topic :  Esli Vy esche v Manchestere, u nas vecherinka russkaya v
    > gorode Bolton v subotu (12.01.2008) ot 18:00 na pabe "Balmoral" (v
    > tsentre).  Stoit vsego 60 funtov, tak, esli pridut N chelovek, prosyat
    > c kazhdogo 60/N funtov.  Mike


    Spasibo :), no ia ne v manchestere uje s 2004
    Vagant, Jan 9, 2008
    #19
  20. Vagant

    Vagant Guest

    On Jan 9, 4:38 pm, wrote:
    > >Well, a reply with a long code which was not asked would not be
    > >helpful either and if one does not like question then just reply
    > >nothing.

    >
    > As I understand it, you have a PhD in nuclear magnetic resonance
    > (Manchester 2004), so FPGAs and the associated HDLs are not beyond
    > your abilities.
    >
    > But, as I said earlier, you need to learn some basic electronics and
    > logic before you can handle these more recent developments, because
    > most of those working with HDLs have that experience of older
    > technologies and what you read will almost always assume that.
    >
    > Did you think it was going to be easy?
    >
    > Mike


    It goes allright with me and I am familiar with electronics. I got
    Diploma in radiophysics and electronics (undegraduate study) but FPGA
    and VHDL are something really new. So sometimes I get stuck and then i
    ask questions here.
    Vagant, Jan 9, 2008
    #20
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