How to write compact DFF chain?

[Davy]

Hi all,

Sometimes I have to write long DFF chain like below:

//------code--------------
....
reg [7:0] DFF0,DFF1,DFF2,...DFF50;

always@(posedge clk)
if(rst)
begin
DFF0 <= 0;
...
DFF50 <= 0;
end
else
begin
DFF0 <= INPUT;
...
DFF50 <= DFF49;
end

//------code end-----------
It's too long, is there any good compact style?

Any suggestions will be appreciated!
Best regards,
Davy

 

[Michael]

You could make another verilog95 way:

reg [8*51-1:0] DFFs;
wire [7:0] DFF0,DFF1,DFF2,...DFF50;
assign {DFF50, DFF49, ..., DFF0} = DFFs;

always @(posedge clk) begin
if(rst) DFFs <= {51{8'h00}};
else begin
DFFs <= DFFs << 8;
DFFs[7:0] <= INPUT;
end
end

Of course you can omit assigning and use only required bits from vector
DFFs.

 

[Thomas Stanka]

Xpost from OP, FUp2 comp.lang.vhdl

Sometimes I have to write long DFF chain like below:

In VHDL you would write

if reset_active then
DFF <= (others =>'0');
elsif rising_edge(Clk)
DFF <= DFF( xxx downto 0) & input;
end if

If you don't like to change to VHDL than you should avoid posting in
the VHDL-group.

bye Thomas