How to write system verilog testbench assertions for a VHDL design

Discussion in 'VHDL' started by zj82119, Oct 21, 2008.

  1. zj82119

    zj82119

    Joined:
    Oct 21, 2008
    Messages:
    1
    I tried to find useful information about this, but didn't succeed.
    Hope to find examples testbench using system verilog here. By the way, how to bind the design witht this testbench? Simulation tool: Questasim.

    Here is one VHDL design. Thanks for providing and testbench using system verilog.

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_arith.ALL;
    USE ieee.std_logic_signed.ALL;
    USE ieee.std_logic_unsigned.ALL;

    ENTITY sig_altmult_accum IS
    PORT (
    a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    clk: IN STD_LOGIC;
    accum_out: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
    ) ;
    END sig_altmult_accum;

    ARCHITECTURE rtl OF sig_altmult_accum IS
    SIGNAL a_reg, b_reg : signed (7 DOWNTO 0);
    SIGNAL pdt_reg : signed (15 DOWNTO 0);
    SIGNAL adder_out : signed (15 DOWNTO 0);
    BEGIN
    PROCESS (clk)
    BEGIN
    IF (clk'event and clk = '1') THEN
    a_reg <= SIGNED (a);
    b_reg <= SIGNED (b);

    pdt_reg <= a_reg * b_reg;
    adder_out <= adder_out + pdt_reg ;
    END IF;
    END process;

    accum_out <= std_logic_vector(adder_out);
    END rtl;
    zj82119, Oct 21, 2008
    #1
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