I can use std_logic_vector only as input signal in Xilinx?

Discussion in 'VHDL' started by Will, Mar 9, 2009.

  1. Will

    Will Guest

    Hi all,

    When I assign an input signal as integer or real, I can only change
    its value as a bit in test bench using Xilinx ISE 9.2i. Is
    std_logic_vector the only right type for an input signal to input an

    Thanks and bow.
    Will, Mar 9, 2009
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  2. joris


    Jan 29, 2009
    A entity "should" have std_logic/std_logic_vector input/outputs only (this is required byt Xilinx ISE anyway)

    You can use integer-type or other types in the test bench, as long as you convert them to/from std_logic_vector for inputs/outputs of the component that's being tested.
    joris, Mar 10, 2009
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