i can't simulate with modelsim XE III 6.2C

Discussion in 'VHDL' started by DaVidL, Jun 14, 2007.

  1. DaVidL

    DaVidL Guest

    hello,

    i wrote a simple vhdl program and i can simulate it. This is how i try it.

    I have a simple vhdl progam written, i just added "c<= a and b" so i can do
    some simulation.
    A add a new source(test bench waveform) to my project.
    (Notice: from now one my ise simulation toolbar is visible but the buttons
    are disabled.)
    I put my testsignals correct.
    and now???

    thanks, DaVidL
    DaVidL, Jun 14, 2007
    #1
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  2. Mike Treseler, Jun 14, 2007
    #2
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  3. DaVidL

    DaVidL Guest

    > Consider using a vhdl simulator.

    You're wright. Thanks for the tip.
    DaVidL, Jun 15, 2007
    #3
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