I solved my problem!!!!

Discussion in 'VHDL' started by Xin Xiao, Jan 12, 2008.

  1. Xin Xiao

    Xin Xiao Guest

    If you read my problem (posted a few days ago), I want to say that I have
    implemented my 64K RAM using RAM blocks and now synthesis takes only 10
    minutes or so. The problem was that my fpga hadn't enough ram blocks, I
    chose another fpga and the problem was solved.

    I happy :)
     
    Xin Xiao, Jan 12, 2008
    #1
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  2. Xin Xiao

    skyhover

    Joined:
    Jan 9, 2008
    Messages:
    2
    congratulations! i have met the similar problem like yours, and your question and the replies help me a lot:)
     
    skyhover, Jan 12, 2008
    #2
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