i2c Start and stop detection

Discussion in 'VHDL' started by VIPS, May 18, 2009.

  1. VIPS

    VIPS Guest

    Hi all

    I am implementing the I2C Slave and I am using the I2C clock SCL for
    detecting the start and stop condition . I am detecting the start and
    stop successfully in simulation but i am not able to do the same in
    the post synthesis scenario. More so I am getting a setup time
    violation for the same in the timing analysis . I am running the I2C
    at a very slow speed of 100KHz.

    The code is below

    process (SDA_IN, START_RST,rst)
    begin
    if rst ='1' then
    STARTOP <='0';
    -- elsif (START_RST = '1') then
    -- STARTOP <= '0';
    elsif (SDA_IN'event and SDA_IN = '0') then
    STARTOP <= scl;
    end if;
    end process;
    ------------------------------------------------------------------------------
    -- stop condition detection
    process (RST, SCL, SDA_IN, STARTOP)
    begin
    if RST = '1' or SCL = '0' or STARTOP='1' then
    STOPOP <= '0';
    elsif SDA_IN = '1' and SDA_IN'event then
    if SCL = '1' then
    STOPOP <= '1';
    end if ;

    end if;
    end process;

    Can any one give me a reliable way to detect the start and stop
    condition that the synthesis tool doesnot give any setup time
    violation. I am not using a high clock for sampling as the requirement
    is to use the SCL only. May be to save board resourse and space.

    Help will be appreciated. I am using Altera max II CPLD and the
    synthesis tool is quartus 9.0

    Thanks

    Vipul
    VIPS, May 18, 2009
    #1
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  2. VIPS wrote:

    > I am implementing the I2C Slave and I am using the I2C clock SCL for
    > detecting the start and stop condition . I am detecting the start and
    > stop successfully in simulation but i am not able to do the same in
    > the post synthesis scenario.


    That scenario requires a synchronous process
    something like this:
    ....
    begin
    if reset = '1' then
    init_regs;
    elsif rising_edge(clock) then
    update_regs;
    end if;
    update_ports;
    end process;

    > Help will be appreciated.


    An i2c controller is a complex shift register
    with case statements for bit and byte control.
    A working design will require several
    hundred lines of code.

    Google a bit. This has been done.

    -- Mike Treseler
    Mike Treseler, May 19, 2009
    #2
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  3. VIPS

    VIPS Guest

    On May 18, 7:12 pm, Mike Treseler <> wrote:
    > VIPS wrote:
    > > I am implementing the I2C Slave and I am using the I2C clock SCL for
    > > detecting the start and stop condition . I am detecting the start and
    > > stop successfully in simulation but i am not able to do the same in
    > > the post synthesis scenario.

    >
    > That scenario requires a synchronous process
    > something like this:
    > ...
    > begin
    >   if reset = '1' then
    >      init_regs;
    >   elsif rising_edge(clock) then
    >      update_regs;
    >   end if;
    >   update_ports;
    > end process;
    >
    > > Help will be appreciated.

    >
    > An i2c controller is a complex shift register
    > with case statements for bit and byte control.
    > A working design will require several
    > hundred lines of code.
    >
    > Google a bit. This has been done.
    >
    >       -- Mike Treseler


    Thanks Mike for the reply . I have implemented the I2C slave as a
    state machine and the start and stop condition in data going from
    high to low when the clock is high . It is working fine in simulation
    but i am stuck up in the start and stop detection condition as it is
    asynchronous and on synthesis itis giving a setup time violation in
    synthesis in quartus. This is the main issue as to design a ckt for
    start and stop condition with I2C clock . I am not using oversampled
    clock as it is desired to use the I2C clock
    VIPS, May 19, 2009
    #3
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