Ideas on higher level design

Discussion in 'VHDL' started by vtxsupport@hotmail.com, Mar 12, 2012.

  1. Guest

    Hi,
    Pleased to introduce my new tool, VTM 2012. It is intended to be a
    table based edit tool for Verilog/VHDL module's interface definition,
    and unify the process of HDL coding and document writing. A demo is at
    http://www.veriloghdl.org/demo.html
    These tools enable you to build the design's framework, both top down
    and bottom up styles. I want to design the HDL in even higher level. I
    would like to get some ideas on how people think it before VTM's
    completeness. I am now considering to add system verilog interface
    feature to it. But I see very few people using system verilog feature
    like interface in their RTL designs. Do you think it a valuable
    feature? Any comment is welcome.
    Thanks
    , Mar 12, 2012
    #1
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  2. On Mon, 12 Mar 2012 08:06:14 -0700, vtxsupport wrote:

    > Hi,
    > Pleased to introduce my new tool, VTM 2012. It is intended to be a table
    > based edit tool for Verilog/VHDL module's interface definition, and
    > unify the process of HDL coding and document writing. A demo is at
    > http://www.veriloghdl.org/demo.html
    > These tools enable you to build the design's framework, both top down
    > and bottom up styles. I want to design the HDL in even higher level. I
    > would like to get some ideas on how people think it before VTM's
    > completeness. I am now considering to add system verilog interface
    > feature to it. But I see very few people using system verilog feature
    > like interface in their RTL designs. Do you think it a valuable feature?
    > Any comment is welcome.
    > Thanks


    I don't know about System Verilog (and you asked on comp.lang.vhdl)
    but I downloaded VTC to play with.

    It can't find any ports at all in the following entity!
    (Which ISE will synthesise -empty- happily enough)

    If I add a std_logic signal, it can find that.
    But if ports are restricted to std_logic[_vector] and not much else, it
    can't exactly claim to support HDL development at a higher level, can it?

    I can only see a demo of the other tool, VTM, and it appears to have no
    way of assigning a type to a port. The field it calls a type, is actually
    a mode in VHDL terminology ( in, out etc). I may be misunderstanding, but
    it seems to me that this tool would enforce VHDL design at a VERY low
    level indeed.

    (Oh and VTC crashed under Wine here. I will have a large blank square in
    the middle of the screen until I reboot...)

    Sorry, but count me as not impressed with the current version.

    - Brian

    ----------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.numeric_std.all;

    package mytypes is

    type inport is record
    data_in : std_logic_vector(7 downto 0);
    ack : std_logic;
    end record;

    type outport is record
    data_out : std_logic_vector(7 downto 0);
    req : std_logic;
    r_wn : std_logic;
    end record;

    end package mytypes;
    ----------------------------------------------------
    library work;
    use work.mytypes.all;

    entity bus_if is
    port
    (
    thing : in integer;
    intack : out boolean;
    -- irq : in std_logic;
    in_bus : in inport;
    out_bus : out outport;
    address : out unsigned(7 downto 0)
    );
    end bus_if;

    architecture beh of bus_if is
    begin
    end beh;
    ----------------------------------------------------
    Brian Drummond, Mar 12, 2012
    #2
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  3. Guest

    Hi Brian,
    Thanks for using and your suggestion. VTC does not support all VHDL features now. As in the user's guide said, it supports only std_logic and std_logic_vector for IO now. At first, these tools are designed for verilog. When transferring to mixed VHDL and verilog support, I found many suggestions that only use these types in IO for max compatibility.
    I am trying to support more VHDL types, for higher level HDL design. I found this could be done together with interface feature in system verilog. So I would like to know what is the favourite usage of them in design field.
    For VTM, it is designed to be extensible. Columns can be defined in the config file. For now, this has not been finished. Only compatible types with verilog is supported.
    For Wine, I succeeded with it in Redhat. You may try to config Wine to OS WindowsXp. Can you tell me your OS and wine version so I can test it. But I cannot guarantee to fix it:)
    Compared to the verification field, I feel few progress in the design fieldfrom EDA vendors. I try to write EDA tools with new ideas. e.g. VTC, I hope it can bring the fastest speed in top level integration. And VTM, I foundno other tool can convert an existed IO table to HDL code. With your support, I can do it better.

    Thanks
    , Mar 15, 2012
    #3
  4. Tricky Guest

    On Thursday, March 15, 2012 3:35:19 PM UTC, wrote:
    > Hi Brian,
    > Thanks for using and your suggestion. VTC does not support all VHDL features now. As in the user's guide said, it supports only std_logic and std_logic_vector for IO now. At first, these tools are designed for verilog. Whentransferring to mixed VHDL and verilog support, I found many suggestions that only use these types in IO for max compatibility.
    > I am trying to support more VHDL types, for higher level HDL design. I found this could be done together with interface feature in system verilog. So I would like to know what is the favourite usage of them in design field.
    > For VTM, it is designed to be extensible. Columns can be defined in the config file. For now, this has not been finished. Only compatible types withverilog is supported.
    > For Wine, I succeeded with it in Redhat. You may try to config Wine to OSWindowsXp. Can you tell me your OS and wine version so I can test it. But I cannot guarantee to fix it:)
    > Compared to the verification field, I feel few progress in the design field from EDA vendors. I try to write EDA tools with new ideas. e.g. VTC, I hope it can bring the fastest speed in top level integration. And VTM, I found no other tool can convert an existed IO table to HDL code. With your support, I can do it better.
    >
    > Thanks


    Other tools have been supporting types other than sl/stv for many years now.. Even simulink can interface to multiple port types via co-simulation and their HDL coder outputs signed and unsigned (the interfacing supports more than their HDL coder - thankfully).

    Before this tool can become any use to anyone, I feel it is essential all port types are supported. Otherwise you're only able to sell to engineers stuck in the 1990s (but there are plenty of engineers still stuck there with VHDL).
    Tricky, Mar 19, 2012
    #4
  5. Guest

    Hi Tricky,
    Thanks for your advice.
    I think you mainly mentioned pure VHDL designs. For Verilog and mixed HDL users, IO types are usually not that many.
    Your opinion is important in developing more features for VHDL, and let me know more scenarios. I hope I can develop more useful features.
    The different idea and the reason for existence of the tool are the operation style and how it can save time. Adding some types' support in language parser can make it more robust. How do you feel the tool's different features from other tools? Free download and quick demo are available on the website. For a starter short demo, please visit http://www.veriloghdl.org/demos/demo1.htm

    Thanks
    , Mar 20, 2012
    #5
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