Identifier "signed" is not directly visible

Discussion in 'VHDL' started by Thom, Apr 11, 2008.

  1. Thom

    Thom

    Joined:
    Apr 11, 2008
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    New to VHDL and need some newbee help...

    Here is the begining of my code:


    ----------------------------------------------------
    library ieee;
    USE ieee.std_logic_1164.all;
    USE work.my_data_types.all;
    use ieee.numeric_std.all;
    use IEEE.std_logic_unsigned.all;
    use ieee.std_logic_arith.ALL;
    use ieee.std_logic_signed.all;
    ----------------------------------------------------
    ENTITY Problem5_4_adder IS
    PORT (add_a, add_b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    add_sel: IN sel_1to0;
    add_cin: IN STD_LOGIC;
    add_cout: OUT STD_LOGIC;
    add_sum: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
    END Problem5_4_adder;
    ----------------------------------------------------
    ARCHITECTURE adder OF Problem5_4_adder IS

    BEGIN
    PROCESS (add_a, add_b, add_sel, add_cin)

    VARIABLE temp0: STD_LOGIC_VECTOR ((7 DOWNTO 0):= (others=> '0');
    VARIABLE temp1: STD_LOGIC_VECTOR ((7 DOWNTO 0):= (others=> '0');
    VARIABLE temp2: SIGNED (7 DOWNTO 0);
    VARIABLE temp3: SIGNED (7 DOWNTO 0);
    VARIABLE temp4: SIGNED (7 DOWNTO 0);
    VARIABLE temp5: SIGNED (8 DOWNTO 0);

    BEGIN

    ----------------------------------------------------

    When I try to compile I get

    Identifier "signed" is not directly visible

    all the libraries load correctly but as soon as it gets to the line with SIGNED in it...What's up with that?
     
    Last edited: Apr 11, 2008
    Thom, Apr 11, 2008
    #1
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