K
Kim Enkovaara
Weng said:Another question is unanswered:
Why unsigned/signed cannot be used in top layer? and why the signals in
the top layer must be std_logic and std_logic_vector?
Usually synthesis creates a toplevel that has only std_logic* signals. And if
you want to simulate netlist without any extra wrappers, it's easiest to use
std_logic also at the RTL top level symbol.
In asics sometimes you still need the wrappers, because the io-pads are done during
the netlist generation in many flows. In that case RTL toplevel does not yet have
three state drivers and simulation wrapper is needed to match the netlist
functionality.
--Kim