if-then vs. if-generate

Discussion in 'VHDL' started by valentin tihomirov, Feb 21, 2004.

  1. Why lables are mandatory for generate statemente? Why *else* cannot be used
    with *generate*? For example, it should be quite typical situation, you have
    two different implementations of the same block depending on a generic.

    B1: if Param1 generate
    ...
    end generate;

    B2: if not Param1 generate
    ...
    end generate;



    Wouldn't it be more neat to allow the following implementation of generate
    block:

    B1: if Param1 generate
    ...
    else
    ...
    end generate;

    ???? Thanks.
    valentin tihomirov, Feb 21, 2004
    #1
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  2. On Sat, 21 Feb 2004 14:11:46 +0200, "valentin tihomirov"
    <> wrote:

    > Why *else* cannot be used
    >with *generate*?


    This is a mistake in the language, and will be fixed in VHDL 200x.
    You will also be able to use 'case-generate'.

    Expect tool support sometime this decade.

    Regards,
    Allan.
    Allan Herriman, Feb 21, 2004
    #2
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  3. Hi,

    valentin tihomirov wrote:
    > Why lables are mandatory for generate statemente?


    I am not sure about the motivation for this restriction
    but I think the reason might be as follows:

    Any components instantiated in the design must get a unique
    instance name. E.g., the VHDL code

    B1: if Param1 generate
    mycomp: entity test port map (....);
    end generate;

    mycomp: entity test port map (....);

    will generate two components named ":B1:mycomp" and ":mycomp".
    If you were allowed to omit "B1" then both components would
    receive the same instance name.

    Of course, one might argue that the LRM could forbid creating
    the same instance name for both components. However, note that
    the generate statement creates a new declarative region.
    E.g., one can write


    architecture test of test is
    constant myconst : integer := 11;
    begin

    B1: if Param1 generate
    -- declares a new constant myconst that
    -- is only visible within the "generate"
    -- region (and overloads the previously
    -- declared constant "myconst").
    -- This is legal in VHDL.
    constant myconst : bit := '1';
    begin
    mycomp: entity test port map (....);
    end generate;

    mycomp: entity test port map (....);

    end test;

    I.e., within the generate statement, new objects/types/... may
    be created that "overload" other declarations with the same
    name. So, defining "mycomp" to be illegal while declaration of
    "myconst" is ok would create some kind of inconsistency.
    Perhaps, this is the reason to make a label mandatory for the
    generate statement.

    Please note that I wasn't involved in the definition of
    the VHDL LRM. So, I'm just guessing...

    --
    Edwin


    >
    > B1: if Param1 generate
    > ...
    > end generate;
    >
    > B2: if not Param1 generate
    > ...
    > end generate;
    >
    >
    >
    > Wouldn't it be more neat to allow the following implementation of generate
    > block:
    >
    > B1: if Param1 generate
    > ...
    > else
    > ...
    > end generate;
    >
    > ???? Thanks.
    >
    >
    Edwin Naroska, Feb 23, 2004
    #3
  4. valentin tihomirov

    electronics gyan`

    Joined:
    Feb 18, 2013
    Messages:
    1
    if and else statement

    if else statement :-

    Syntax:
    if then
    statements
    ...
    [
    elsif then
    statements
    ...
    else
    statements
    ...
    ]
    endif;

    from :-
    electronicsgyan.com
    Last edited: Feb 18, 2013
    electronics gyan`, Feb 18, 2013
    #4
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