IIR filter implementation on FPGA

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Hi there,

I am implementing an IIR butterworth lowpass filter on FPGA. I have already done it in MATLAB/SIMULINK and now implementing it in VHDL. I have to use fixed-point arithmetic for my filter coefficients and the input output. I am taking 16-bit input with 15-bit fractional part and 1 sign bit and 16-bit output with 1 sign bit , 4 integer bits and 11 fractional bits. and the same wordlength of 16-bits for coefficients (1 sign bit, 1-bit (or 2 for a couple of them) inetger part and 14-bits (or 13-bit for a couple of them) fractional part.). I was having problems with it but now, I have converted the coefficients to signed fixed-point binary format. So, just using them as constants.

I already have the fixed point values for the coefficients and as they're just 5 coefficients, I have just taken them as constants. Do you think it is alright? Well, then I am giving input(16-bit {1 sign bit and 15 fractional bits}) from the switches and buttons on the Spartan-3 board. As there are just 4 1-bit push buttons and an 8-bit switch (12-bits altogether, and then I am keeping 4 bits constant). Then the output is also 16-bit which includes 1 sign bit, 4 integer bits and 11 fractional bits. Now, I have used the 7-segment display to show the output in such a way that the leftmost digit is showing the hex value of 4 integer bits, and then a dot to show decimal point and then the next 3 digits for fractional part but as there are 11-bits in fractional part, so, I have padded a zero at the end of fractional part just to make it a 4-bit value for the hex-decoder. And then I am using the last dp (dot/decimal point on 7-seg display to indicate the sign of the number).

So, I am only giving input from the board and getting the output and not using any RAM/ROM or multiplier blocks, I have only used constants and the operators ('+', '-', '*') and left it all to the VHDL to do all the intermediate arithmetic and use the hardware components as required, will it be fine?

Do you think it is a good design?

Now, I was wondering what will be the best option if I wanted to demonstrate the filter operation more clearly. I mean these are just numbers that I am showing on the 7-seg display. But if I want to give a sinusoidal input and get a filtered waveform at the output.

1)I have got the code for vhdl sine generator.
2)Showing the ouput on the oscilloscope? it sounds a bit tedious.
3)Do you think interfacing a microphone and speaker would work for this design (and for Spartan-3)?
4)Or giving the output back to the simulator and showing the waveform would do?
5)or any other application/test case you would suggest for IIR filter implementation on FPGA?
Thanks very much for your help.

Regards,

Kami
 
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Hey guys,
Give some response at least please?
It looks like nobody's viewed my post?
 
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VHDL IIR filter implementation using FPGA

Sir,
Please give me necessary information on the titled topic
 
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Please give details on IIR filter implementation using fpga.The system is having an AC content of 200 Hz and 200 mV amplitude while it is provided with a nearly DC content of less than 5 Hz of amplitude 4V. The sampling frequency is 10KHz and clock frequency is 10MHz The requirement is to remove the AC component.Also add some information regarding matlab and VHDL programs
 

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