Illegal concurrent statement?

Discussion in 'VHDL' started by Philipp, Jul 4, 2008.

  1. Philipp

    Philipp Guest

    Hi

    I wanna evaluate for each bit in the std_logic_vector I(14 downto 0) the
    following espression:


    for I in 0 to 14 loop
    RanIB_tmp(I) <= '1' when
    ((DST(I)(conv_integer(std_logic_vector(OLD_Dest)))='1')
    and
    (CDT(conv_integer(std_logic_vector(OLD_Dest)))='1'))
    else '0';
    end loop;

    However, when I try to run the code it tells me that I am using an
    illegal concurrent statement? Anyone an idea how I could write this in
    an loop so that I can save some copy & paste?

    many thanks
    Philipp
     
    Philipp, Jul 4, 2008
    #1
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  2. Philipp wrote:

    > However, when I try to run the code it tells me that I am using an
    > illegal concurrent statement?


    Maybe you forgot to put the loop inside a process.
     
    Mike Treseler, Jul 4, 2008
    #2
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  3. Philipp

    Guest

    On Jul 4, 12:14 pm, Mike Treseler <> wrote:
    > Philipp wrote:
    > > However, when I try to run the code it tells me that I am using an
    > > illegal concurrent statement?

    >
    > Maybe you forgot to put the loop inside a process.


    It looks like the original signal assignment was a concurrent
    assignment, which is OK on its own inside an architecture body.
    Changing the "for ... loop... end loop", which is a sequential form,
    into a "for ... generate ... end generate", which is a concurrent
    statement, should make this construct OK in the same context.

    - Kenn
     
    , Jul 4, 2008
    #3
  4. Philipp

    Dal Guest

    The 'when ... else ...' is a concurrent signal assignment. If your
    code is in a process then changing it to a 'if ... then ... else ...'
    should fix the problem. If not in a process then using a generate as
    suggested should also fix the problem.

    Darrin
     
    Dal, Jul 6, 2008
    #4
  5. Philipp

    Luc Guest

    I think recoding to:

    for I in 0 to 14 loop
    if (DST(I09conv_integer(std_logic_vector(OLD_Dest)))='1')
    and
    (CDT(conv_integer(std_logic_vector(OLD_Dest)00='1')) then
    RANIB_tmp(I) <= '1';
    else
    RanIB_tmp(I) <= '0';
    end if;
    end loop;

    this should do it. Both are now sequential statements ( need to place
    in a process)
    Otherwise use generate ... statement as posted before

    Luc

    On Fri, 04 Jul 2008 16:26:57 +0100, Philipp <>
    wrote:

    >Hi
    >
    >I wanna evaluate for each bit in the std_logic_vector I(14 downto 0) the
    >following espression:
    >
    >
    > for I in 0 to 14 loop
    > RanIB_tmp(I) <= '1' when
    > ((DST(I)(conv_integer(std_logic_vector(OLD_Dest)))='1')
    > and
    > (CDT(conv_integer(std_logic_vector(OLD_Dest)))='1'))
    > else '0';
    > end loop;
    >
    >However, when I try to run the code it tells me that I am using an
    >illegal concurrent statement? Anyone an idea how I could write this in
    >an loop so that I can save some copy & paste?
    >
    >many thanks
    >Philipp
     
    Luc, Jul 22, 2008
    #5
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