implement a 2 resisters A,B comparison (structural)

Discussion in 'VHDL' started by lucahtc, May 18, 2010.

  1. lucahtc

    lucahtc

    Joined:
    May 18, 2010
    Messages:
    6
    what's the way to recognize the minimum register (unsigned) in a vhdl structural mode, by using only gates blocks?

    example (if A<B than Y=1):

    A = 1100
    B = 0111
    Y = 0
    lucahtc, May 18, 2010
    #1
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  2. lucahtc

    joris

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    Jan 29, 2009
    Messages:
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    This should work:
    Code:
    entity cmp is -- if A<B than Y=1 else Y=0
      generic(n : natural);
      port(A, B: in std_logic_vector(n - 1 downto 0);
           Y : out std_logic);
    end cmp;
    
    architecture RTL of cmp is
      signal sY, set : std_logic_vector(n downto 0);
      signal test : std_logic_vector(n - 1 downto 0);
    begin
      sY(n) <= '0';
      set(n) <= '1';
    
    compare: for i in A'range generate
      test(i) <= (A(i) xor B(i)) and set(i + 1);
      sY(i) <= B(i) when test(i) = '1' else sY(i + 1);
      set(i) <= '0' when test(i) = '1' else set(i + 1);
    end generate compare;
    
      Y <= sY(0);
    end RTL;
    
    Note that I didn't replace the when/else construct with mux'es.
    Writing them explicitly obviously forces to fix the value of 'n'
    joris, May 18, 2010
    #2
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  3. lucahtc

    joris

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    Jan 29, 2009
    Messages:
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    BTW, I realised the multiplexer statement I made was wrong - this is a version with the mux written explicitly:

    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    
    entity cmp is -- if A<B than Y=1 else Y=0
      generic(n : natural);
      port(A, B: in std_logic_vector(n - 1 downto 0);
           Y : out std_logic);
    end cmp;
    
    architecture structural of cmp is
      signal sY, set, test : std_logic_vector(n - 2 downto 0);
    begin
      sY(n - 2) <= (not A(n - 1)) and B(n - 1);
      set(n - 2) <= A(n - 1) xnor B(n - 1);
    
    compare: for i in n - 2 downto 1 generate
      test(i) <= (A(i) xor B(i)) and set(i);
      sY(i - 1) <= ((not test(i)) and sY(i)) or (test(i) and B(i));
      set(i - 1) <= (not test(i)) and set(i);
    end generate compare;
    
      test(0) <= (A(0) xor B(0)) and set(0);
      Y <= ((not test(0)) and sY(0)) or (test(0) and B(0));
    
    end structural;
    
    Last edited: May 18, 2010
    joris, May 18, 2010
    #3
  4. lucahtc

    lucahtc

    Joined:
    May 18, 2010
    Messages:
    6
    thank you very much, works great.
    I have another problem, im doing a structure style that should count the number of ones in a register, but without success.
    Do you have any suggestions on how to do do that?
    lucahtc, May 19, 2010
    #4
  5. lucahtc

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    Uhmm a popcount, have done some of that, though would have to adapt a bit for structural code.
    What I did was, first a number of one bit-counts, then two-bit counts of the results, then four-bit counts (requiring log(n) additions)
    joris, May 19, 2010
    #5
  6. lucahtc

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    BTW, I tested with the Xilinx synthesis tool, The idiom I posted didn't give the same performance as,
    Y <= '1' when unsigned(A) < unsigned(B) else '0'
    (for a given fpga target)

    I'm not sure how to get the performance equal to what it does -- would be interested in seeing code performing the same as well!
    joris, May 19, 2010
    #6
  7. lucahtc

    lucahtc

    Joined:
    May 18, 2010
    Messages:
    6
    ive done the ones counter by 2 generate cicles with half adders, it works.

    i dont know other method to do the comparator, for my application this is enough, but if you figure out how to make it better im interested too
    lucahtc, May 19, 2010
    #7
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