Implementation of Register File VHDL Model

Discussion in 'VHDL' started by New User ^_^, Apr 20, 2004.

  1. New User ^_^

    New User ^_^ Guest

    Hi Everyone,

    At the moment, I am making a regfile VHDL model but I have no idea how
    to make it. I would be very grateful if any of you could give me a
    simple example, better with some explanation as you all know that it
    is quite difficult.

    Thanks a lot!!

    Chicken Wing
     
    New User ^_^, Apr 20, 2004
    #1
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  2. New User ^_^

    fabbl Guest

    try this:

    subtype LONGWORD is std_logic_vector (31 downto 0);
    type LONGWORD _ARRAY is array (integer range <>) of LONGWORD;

    type VHDLRECORD is
    record
    data1 :LONGWORD _ARRAY (0 to 15);
    data2: LONGWORD _ARRAY (0 to 15);
    end record;

    signal my_regfile: VHDLRECORD;

    then to access it:
    my_regfile.data1(3)<=x"DEADBEEF";

    "New User ^_^" <> wrote in message
    news:...
    > Hi Everyone,
    >
    > At the moment, I am making a regfile VHDL model but I have no idea how
    > to make it. I would be very grateful if any of you could give me a
    > simple example, better with some explanation as you all know that it
    > is quite difficult.
    >
    > Thanks a lot!!
    >
    > Chicken Wing
     
    fabbl, Apr 21, 2004
    #2
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  3. New User ^_^

    Jluis Guest

    there are many ways to implement it, so I design this register file
    with 8 registers and 22 bits long word, I used Max plus and up1 board
    from Altera, hope to help you.

    JLuis
    Mexico
    Center For Research in Mathematics

    -- REGISTER FILE February 19th, 2004 José Luis
    Fernández Jiménez

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.all;
    USE IEEE.STD_LOGIC_ARITH.all;
    USE IEEE.STD_LOGIC_UNSIGNED.all;

    ENTITY regfile IS

    PORT(
    clk: IN std_logic;
    Ra, Rb : IN std_logic_vector(2 DOWNTO 0); --Rc
    rRFA, rRFB, rRF, wRFA: IN std_logic; --rRFC, wRFB, Rfc
    RFdin: IN std_logic_vector(21 DOWNTO 0);
    Rfaout, Rfbout: OUT std_logic_vector(21 DOWNTO 0)); --RFcout


    END regfile;

    ARCHITECTURE archregfile OF regfile IS
    SIGNAL reg0,reg1, reg2, reg3,reg4, reg5, reg6, reg7:
    std_logic_vector(21 DOWNTO 0);
    --SIGNAL tempa, Rfbout, tempc: std_logic_vector(21 DOWNTO 0);
    BEGIN

    WRITE: PROCESS (clk, wRFA) --WRITE PROCESS --wRFB
    BEGIN
    IF clk 'EVENT AND clk= '1' THEN
    IF wRFA = '1' THEN
    CASE Ra IS
    WHEN "000" => reg0 <= RFdin;
    WHEN "001" => reg1 <= RFdin;
    WHEN "010" => reg2 <= RFdin;
    WHEN "011" => reg3 <= RFdin;
    WHEN "100" => reg4 <= RFdin;
    WHEN "101" => reg5 <= RFdin;
    WHEN "110" => reg6 <= RFdin;
    WHEN "111" => reg7 <= RFdin;
    WHEN OTHERS => NULL;
    END CASE;
    END IF;
    END IF;

    END PROCESS WRITE;



    READ: PROCESS (Ra, Rb, rRFA, rRFB, rRF) --READ PROCESS, Rc, rRFC
    BEGIN
    IF rRFA = '1' THEN
    CASE Ra IS
    WHEN "000" => Rfaout <= reg0;
    WHEN "001" => Rfaout <= reg1;
    WHEN "010" => Rfaout <= reg2;
    WHEN "011" => Rfaout <= reg3;
    WHEN "100" => Rfaout <= reg4;
    WHEN "101" => Rfaout <= reg5;
    WHEN "110" => Rfaout <= reg6;
    WHEN "111" => Rfaout <= reg7;
    WHEN OTHERS => Rfaout <= "XXXXXXXXXXXXXXXXXXXXXX";
    END CASE;

    ELSIF rRFB = '1' THEN
    CASE Rb IS
    WHEN "000" => Rfbout <= reg0;
    WHEN "001" => Rfbout <= reg1;
    WHEN "010" => Rfbout <= reg2;
    WHEN "011" => Rfbout <= reg3;
    WHEN "100" => Rfbout <= reg4;
    WHEN "101" => Rfbout <= reg5;
    WHEN "110" => Rfbout <= reg6;
    WHEN "111" => Rfbout <= reg7;
    WHEN OTHERS => Rfbout <= "XXXXXXXXXXXXXXXXXXXXXX";
    END CASE;

    -- ELSIF rRFC = '1' THEN
    -- CASE Rc IS
    -- END CASE;

    ELSIF rRF = '1' THEN
    CASE Ra IS
    WHEN "000" => Rfaout <= reg0;
    WHEN "001" => Rfaout <= reg1;
    WHEN "010" => Rfaout <= reg2;
    WHEN "011" => Rfaout <= reg3;
    WHEN "100" => Rfaout <= reg4;
    WHEN "101" => Rfaout <= reg5;
    WHEN "110" => Rfaout <= reg6;
    WHEN "111" => Rfaout <= reg7;
    WHEN OTHERS => Rfaout <= "XXXXXXXXXXXXXXXXXXXXXX";
    END CASE;

    CASE Rb IS
    WHEN "000" => Rfbout <= reg0;
    WHEN "001" => Rfbout <= reg1;
    WHEN "010" => Rfbout <= reg2;
    WHEN "011" => Rfbout <= reg3;
    WHEN "100" => Rfbout <= reg4;
    WHEN "101" => Rfbout <= reg5;
    WHEN "110" => Rfbout <= reg6;
    WHEN "111" => Rfbout <= reg7;
    WHEN OTHERS => Rfbout <= "XXXXXXXXXXXXXXXXXXXXXX";
    END CASE;

    END IF;
    END PROCESS READ;

    END archregfile;
     
    Jluis, Apr 21, 2004
    #3
  4. New User ^_^

    sammy

    Joined:
    Aug 2, 2009
    Messages:
    1
    //Register of 2 bit

    library ieee;
    use ieee.std_logic_1164.all;
    entity register is
    port( D: in std_logic_vector(1 downto 0);
    clk : in std_logic;
    reset : in std_logic;
    load : in std_logic;
    Q : out std_logic_vector(1 downto 0));

    architecture DFF of register is

    begin
    process (Clk,reset)
    begin
    if(reset=1) then
    Q<="00";
    elsif clk'event and clk then
    if(load='1') then
    Q<=D;
    end if;
    end if;
    end DFF;
     
    sammy, Aug 2, 2009
    #4
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