Implementing division operation.

[bhargava.ram]

Hello, I am designing a SDRAM Controller with variable burst size (burst size is an input along with read or write commands), at a point I have to find the number of read operations are needed to calculate the number of times the CAS latency has to be insured along with the precharge time ....

For this I have to divide Burst size input with the maximum of columns a row has. I have tried implementing the repeated subtraction logic but all this has to be done in 1 clock.

1. I have implemented in data flow model as
"alt_result <= conv_std_logic_vector((conv_integer(Burst_size) / conv_integer(Row_size)),8);"

Here the prob is for a value 136 Burst_size and 15 to Row_size I get 9, but 1 word is left and should be written to Row a total, you can say that it would be be ten when you consider 0 to 9 but this is not valid when 135 is divided by 15.

2. I have tried to implement using while loop and for loop but both logics consumed more than 1 clock..

How should I approach ??

Also please could you tell me a book for VHDL other than Bhasker or Perry, which deals from introduction of VHDL commands and taking it to Sythesisable code and test bench implementation like in detail..

Thank You.