implmenting digital backend of RFID tag

Discussion in 'VHDL' started by shakeelsultan, Oct 11, 2006.

  1. shakeelsultan

    shakeelsultan

    Joined:
    Oct 4, 2006
    Messages:
    4
    HI!

    i got a project concerning implementation of "Digital backend of RFID-tag"
    Can anybody help me how to start it? considerationsa etc...
    shakeelsultan, Oct 11, 2006
    #1
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  2. shakeelsultan

    Daniel Kho

    Joined:
    Oct 11, 2006
    Messages:
    4
    You should start with the normal top-down design, identifying the top-level entity and work from there. You may have a top-level entity named RFID_TxRx for the transceiver block for each RFID tag, then create components for the transceiver in a package or other VHDL files. You may have a Tx (transmitter) block, and a Rx (receiver) block as components in the package.

    You may even want to create different subcomponents of the transmitters and receivers as different entities in different files. For example, you may have a transmitter subblock created as <entity scrambler>, and a receiver subblock created as <entity descrambler>.

    Or you may even have something like <entity protocol_codec> or <entity serdes> which are shared by both transmitter and receiver. These are just my ideas to give you a headstart, you may have other ideas which you'll like to implement.

    You may try the following. I haven't tried it yet, and I don't guarantee this structure will work. You should have more files and components than just RFID_Tx and RFID_Rx.


    ---- top-level file (RFID.vhdl) ----
    ---- RFID transceiver ----
    library ieee, work;
    use ieee.std_logic_1164.all;
    use work.rfid.all;

    entity RFID_TxRx is port(...); end RFID_TxRx;

    architecture structural of RFID_TxRx is
    component RFID_Tx is port(...); end component;
    component RFID_Rx is port(...); end component;
    --declare constants/variables/signals here
    begin
    --connect (map) lower-level entities to top-level entity
    Tx: RFID_Tx port map(...);
    Rx: RFID_Rx port map(...);
    end structural;

    ---- package rfid.vhdl ----
    ---- declare all subcomponents in the design in a package ----
    -- library utilisations declared here
    package rfid is
    component RFID_Tx port(...); end component;
    component RFID_Rx port(...); end component;
    end rfid;

    ---- define entities in separate files ----
    ---- RFID_Tx.vhdl ----
    library ieee;
    use ieee.std_logic_1164.all;
    -- other library utilisations here
    entity rfid_tx is port(...); end rfid_tx;

    architecture behaviour of rfid_tx is
    -- signal and variable declarations
    begin
    -- define transmitter behaviour here
    end behaviour;

    ---- RFID_Rx.vhdl ----
    library ieee;
    use ieee.std_logic_1164.all;
    -- other library utilisations here
    entity rfid_rx is port(...); end rfid_rx;

    architecture behaviour of rfid_rx is
    -- signal and variable declarations
    begin
    -- define receiver behaviour here
    end behaviour;
    Last edited: Oct 11, 2006
    Daniel Kho, Oct 11, 2006
    #2
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