Importing Structural VHDL into Cadence 4.4.6

Discussion in 'VHDL' started by Marcus Schaemann, Sep 17, 2003.

  1. Hello,

    I want to import my VHDL design (see below) into Cadence.
    Synthesis with Synopsys Design Compiler creates a structural VHDL
    description.
    I don't have much experience with Cadence, but I have Cadence libraries
    with schematics and layout for the cell IN1, so I think I should be able

    to import the structural VHDL into cadence. But vhdlin returns:

    duluth: *E,1024: intermediate file path
    /usr/local/cadence-ic446/tools/leapfrog/files/STD.ship/standard for
    package STD.STANDARD (AST) does not exist.

    I think I got a problem with the environment setting for the standard
    package.
    Questions:

    - Does anybody has a hint for me where to find the right package
    in the cadence installation or in the technology libraries?
    - How must I modify my cds.lib or vhdl code?
    - Anybody got more information about the Europractice Design Flow?

    Thanks,

    Marcus

    System Environment:
    -------------------

    Synopsys: 2001.08
    Cadence: 4.4.6
    Technology: AMS HIT-KIT v3.4, 0.35 CMOS (through Europractice v13.0)

    cds.lib:
    --------

    INCLUDE /usr/local/cadence-ic446/share/cdssetup/cds.lib
    INCLUDE $AMS_DIR/artist/HK_0.35/cds.lib
    DEFINE sample /usr/local/cadence-ic446/tools/dfII/samples/cdslib/sample
    DEFINE std /usr/local/cadence-ic446/tools/leapfrog/files/STD.ship
    DEFINE IEEE /usr/local/cadence-ic446/tools/leapfrog/files/IEEE.ship

    inv.vhd:
    --------

    library IEEE;
    use IEEE.std_logic_1164.all;

    entity inv is
    port (
    A : in std_logic;
    Y : out std_logic);
    end inv;

    architecture data_flow of inv is
    begin
    Y <= not A;
    end data_flow;

    inv_syn.vhd:
    ------------

    library IEEE;
    use IEEE.std_logic_1164.all;
    library HRDLIB;
    use HRDLIB.all;

    entity inv is
    port( A : in std_logic; Y : out std_logic);
    end inv;

    architecture GAT of inv is
    begin
    U7 : IN1 port map( A => A, Q => Y)
    end GAT;
     
    Marcus Schaemann, Sep 17, 2003
    #1
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  2. Hi,
    Marcus Schaemann wrote:
    > Hello,

    ....
    > cds.lib:
    > --------
    >
    > INCLUDE /usr/local/cadence-ic446/share/cdssetup/cds.lib

    add:
    INCLUDE /usr/local/cadence-ic446/tools/leapfrog/files/cds.lib
    > INCLUDE $AMS_DIR/artist/HK_0.35/cds.lib
    > DEFINE sample /usr/local/cadence-ic446/tools/dfII/samples/cdslib/sample

    and remove these two (they are defined in the cds.lib above)
    > DEFINE std /usr/local/cadence-ic446/tools/leapfrog/files/STD.ship
    > DEFINE IEEE /usr/local/cadence-ic446/tools/leapfrog/files/IEEE.ship
    >

    HTH

    -Eyck
     
    Eyck Jentzsch, Sep 17, 2003
    #2
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