Y
yeah
here plz give up the idea about use of modeling layer in PSL and its
structure
structure
yeah said:here plz give up the idea about use of modeling layer in PSL and its
structure
HT-Lab said:AFAIK the modelling layer just specifies that you can use synthesisable VHDL
constructs inside a PSL unit. This was added to allow users to model
hardware that is not part of the design but is required for verification.
example:
vunit my_prop(arch(entity)) {
property....
process -- sequential
begin
....
end process;
generate -- concurrent
...
end generate
}
Hans
www.ht-lab.com
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