IN the PSL...

Discussion in 'VHDL' started by yeah, Apr 3, 2007.

  1. yeah

    yeah Guest

    here plz give up the idea about use of modeling layer in PSL and its
    structure
     
    yeah, Apr 3, 2007
    #1
    1. Advertising

  2. yeah

    HT-Lab Guest

    "yeah" <> wrote in message
    news:...
    > here plz give up the idea about use of modeling layer in PSL and its
    > structure
    >


    AFAIK the modelling layer just specifies that you can use synthesisable VHDL
    constructs inside a PSL unit. This was added to allow users to model
    hardware that is not part of the design but is required for verification.

    example:

    vunit my_prop(arch(entity)) {
    property....
    process -- sequential
    begin
    ....
    end process;
    generate -- concurrent
    ...
    end generate
    }

    Hans
    www.ht-lab.com
     
    HT-Lab, Apr 3, 2007
    #2
    1. Advertising

  3. yeah

    yeah Guest

    hi
    thanx..
    now its clear...
    HT-Lab wrote:
    > "yeah" <> wrote in message
    > news:...
    > > here plz give up the idea about use of modeling layer in PSL and its
    > > structure
    > >

    >
    > AFAIK the modelling layer just specifies that you can use synthesisable VHDL
    > constructs inside a PSL unit. This was added to allow users to model
    > hardware that is not part of the design but is required for verification.
    >
    > example:
    >
    > vunit my_prop(arch(entity)) {
    > property....
    > process -- sequential
    > begin
    > ....
    > end process;
    > generate -- concurrent
    > ...
    > end generate
    > }
    >
    > Hans
    > www.ht-lab.com
     
    yeah, Apr 4, 2007
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. ben cohen
    Replies:
    2
    Views:
    563
    annytom
    Dec 21, 2003
  2. ben cohen
    Replies:
    0
    Views:
    791
    ben cohen
    Jan 27, 2004
  3. Kumar Vijay Mishra

    PSL pros and cons

    Kumar Vijay Mishra, Sep 29, 2004, in forum: VHDL
    Replies:
    2
    Views:
    2,599
    vhdlcohen
    Oct 2, 2004
  4. Eric DELAGE
    Replies:
    2
    Views:
    727
  5. Eric DELAGE
    Replies:
    2
    Views:
    683
Loading...

Share This Page