inc2modL architecture

Discussion in 'VHDL' started by Loppy, Aug 19, 2006.

  1. Loppy

    Loppy Guest

    I need help, please, for write a simple architecture.

    The entity for this architecture is:

    entity inc2modL is
    port ( entrada : in std_logic_vector(7 downto 0);
    modulo : in std_logic_vector(7 downto 0);
    reset : in std_logic;
    clock : in std_logic;
    salida : out std_logic_vector(7 downto 0)
    );
    end inc2modL;

    the objective of this entity is:

    salida = (entrada + 2) mod (modulo)


    Anybody can help me?.

    Thanks
     
    Loppy, Aug 19, 2006
    #1
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  2. Loppy

    Loppy Guest

    Loppy ha escrito:

    > I need help, please, for write a simple architecture.
    >
    > The entity for this architecture is:
    >
    > entity inc2modL is
    > port ( entrada : in std_logic_vector(7 downto 0);
    > modulo : in std_logic_vector(7 downto 0);
    > reset : in std_logic;
    > clock : in std_logic;
    > salida : out std_logic_vector(7 downto 0)
    > );
    > end inc2modL;
    >
    > the objective of this entity is:
    >
    > salida = (entrada + 2) mod (modulo)
    >
    >


    sorry,

    mod is the rest of a division.

    for example:

    entrada := "00000111";
    modulo := "00000100";

    salida will be "00000001"

    > Anybody can help me?.
    >
    > Thanks
     
    Loppy, Aug 19, 2006
    #2
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