Including Verilog parameter file in VHDL design

[ALuPin]

Hi newsgroup,

I am trying to write a VHDL wrapper for a Verilog IP core which
includes
a "params.v" file:


`define DDR2_MODE
`define ROW_WIDTH 13
`define COL_WIDTH 10
`define COL_WIDTH_EQ_10 TRUE
....

These parameters are used to define the port widths etc. of the IP
core.

How can I take over the parameter file into my VHDL wrapper ?
Do I have to generate a second VHDL parameter file ?

Thank you for your opinion.

Rgds
Andre

 

[Marcus Harnisch]

Hi Andre

I am trying to write a VHDL wrapper for a Verilog IP core which
includes a "params.v" file:

...

How can I take over the parameter file into my VHDL wrapper ?
Do I have to generate a second VHDL parameter file ?

Several options:

1. Do you really have to have a VHDL wrapper? Depending on the amount
of glue logic, the easiest way would be to whip up a Verilog
wrapper and include "params.v" there. It sounds like you will end
up with a mixed language environment anyway.

2. At least one tool I know of can output the interface description of
a compiled design in XML format. You can get really fancy and write
an XSLT script to generate a VHDL wrapper :^)

Or use something like Perl's XML::Simple.

3. Maybe your tools support something like "cc -E" in C-world, which
gives you the preprocessed output of a processed file. Then you
could use these macros (not parameters in Verilog jargon!) in your
VHDL file.

4. Roll your own (limited) Verilog preprocessor in your favorite
scripting language.

Regards,
Marcus

--
note that "property" can also be used as syntaxtic sugar to reference
a property, breaking the clean design of verilog; [...]

-- Michael McNamara
(http://www.veripool.com/verilog-mode_news.html)