Increasing the Global Clock value inside the design ?

Discussion in 'VHDL' started by anil, Jun 10, 2005.

  1. anil

    anil Guest

    Hello,

    I have a question relating to Clocks. If i have a clock with
    frequency Fs . I want to generate another clock with frequency N*Fs.
    How is this done in VHDL.

    or is it that i must have another clock input with this frequency.

    also suggest me which method is the better of the above two .

    Thanking you in advance.

    Regards,
    J.Anil Kumar.
     
    anil, Jun 10, 2005
    #1
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  2. anil

    Eric Guest

    With any descriptive langauge (VHDL, Verilog) you can't generate a
    clock faster than the one used in the sensitivity list.

    You could use both rising and falling edge to create a 2x clock, but
    I've read that using both edges is not good practice for synthesis.

    You could instantiate a Xilinx DCM and use that to multiply the clock,
    or an Altera PLL. These are hardware blocks built into the FPGA's that
    allow for clock multiplication/ division.

    Eric
     
    Eric, Jun 10, 2005
    #2
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  3. anil wrote:
    > I have a question relating to Clocks. If i have a clock with
    > frequency Fs . I want to generate another clock with frequency N*Fs.
    > How is this done in VHDL.
    >
    > or is it that i must have another clock input with this frequency.
    >
    > also suggest me which method is the better of the above two .


    IMHO, if you're targetting an FPGA, you're better of having your highest
    frequency clock come straight in - you can multiply clocks using hard IP
    blocks (DCMs, PLLs etc), but certainly in the case of Xilinx DCMs, you
    increase the jitter, sometimes quite dramatically. It's a lot easier to
    divide the clocks down afterwards.

    The other point is that you can write a synthesisable desciption of
    something that will multiply your clocks, but practically this would
    require particularly special attention to layout and design (ie feedback
    etc), and would generally be considered to be a Bad Idea (Depends too
    much on PVT and requires very careful analysis in order to both specify
    and get what you want). This would not so much be a pure 'vhdl'
    description though, as it would be dependant on factors like the
    physical delay of LUTS and routing.

    my 2c
    Jeremy
     
    Jeremy Stringer, Jun 17, 2005
    #3
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