Independent processes

Discussion in 'VHDL' started by john, Jan 9, 2006.

  1. john

    john Guest

    Hello,

    I have interfaced a 8 bit parallel data bus and a clock signal of the
    USB device to a CPLD. I need to store 32bits of data in a buffer. And
    then serially shift out the 32 bits. The loading of the data into the
    buffer can only be done by using the clock coming from the USB device
    because when USB generates data it generates clock with it. So I
    decided to use another clock to serial out the data. The problem is the

    handshaking between the USB process and the serial out process. The two

    processes have different clocks so the serial out process could miss
    the signal form the USB process that the buffer is ready to be serial
    out. The USB device only provides clock and the data, no hand shaking
    signals.

    Please advice a solution, thanks


    John
     
    john, Jan 9, 2006
    #1
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  2. Mike Treseler, Jan 9, 2006
    #2
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  3. john

    john Guest

    Hi,

    Thanks for the reply! But do not have "we" signal or input pin
    available. Please advice.

    John
    Mike Treseler wrote:
    > john wrote:
    >
    > > I have interfaced a 8 bit parallel data bus and a clock signal of the
    > > USB device to a CPLD.

    >
    > I liked Ray's answer:
    >
    > http://groups.google.com/groups?q=fpga usb_clk toggle_ff
     
    john, Jan 10, 2006
    #3
  4. john

    john Guest

    Hi,

    Thanks for the reply! But do not have "we" signal or input pin
    available. Please advice.

    John
    Mike Treseler wrote:
    > john wrote:
    >
    > > I have interfaced a 8 bit parallel data bus and a clock signal of the
    > > USB device to a CPLD.

    >
    > I liked Ray's answer:
    >
    > http://groups.google.com/groups?q=fpga usb_clk toggle_ff
     
    john, Jan 10, 2006
    #4
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