"Independent" Simulation of Xilinx Project

[russ]

We are doing a simple pld using Xilinx ISE 9.2i. The project began with
9.2i and must be finished with 9.2i.

We are working under DO-254 and need to do either tool qualification or
independent verification and validation with another tool set. GHDL and
GTKWave have been chosen as the second tool set. But the customer
objects that we are still using the Xilinx VITAL, primsim, etc., libraries.

Is there an independent implementation of these libraries for GHDL?
I've googled and got lots of links, but sorting through them hasn't
revealed much yet.

Thanks

 

[Andy Peters]

We are doing a simple pld using Xilinx ISE 9.2i. The project began with
9.2i and must be finished with 9.2i.

We are working under DO-254 and need to do either tool qualification or
independent verification and validation with another tool set. GHDL and
GTKWave have been chosen as the second tool set. But the customer
objects that we are still using the Xilinx VITAL, primsim, etc., libraries.

Is there an independent implementation of these libraries for GHDL?
I've googled and got lots of links, but sorting through them hasn't
revealed much yet.

Sounds like your customer is the typical military type with his head
up his ass.

-a

 

[HT-Lab]

We are doing a simple pld using Xilinx ISE 9.2i. The project began with
9.2i and must be finished with 9.2i.

We are working under DO-254 and need to do either tool qualification or
independent verification and validation with another tool set. GHDL and
GTKWave have been chosen as the second tool set. But the customer
objects that we are still using the Xilinx VITAL, primsim, etc.,
libraries.

Is there an independent implementation of these libraries for GHDL?
I've googled and got lots of links, but sorting through them hasn't
revealed much yet.

Sounds like your customer is the typical military type with his head
up his ass.

very good, there isn't enough humour on this newsgroup

Russ, I would suggest you contact your DER and discuss the tools issue
before going on a tangent with GHDL.

Hans
www.ht-lab.com

 

[goouse]

We are doing a simple pld using Xilinx ISE 9.2i. The project began with
9.2i and must be finished with 9.2i.

We are working under DO-254 and need to do either tool qualification or
independent verification and validation with another tool set. GHDL and
GTKWave have been chosen as the second tool set. But the customer
objects that we are still using the Xilinx VITAL, primsim, etc., libraries.

Is there an independent implementation of these libraries for GHDL?
I've googled and got lots of links, but sorting through them hasn't
revealed much yet.

Thanks

Hi russ,
maybe you can point out to your customer, that libraries are part of
the source code, not of the simulator tools.
The mentioned libs are a description of the hardware you are using,
and therefore as unique as your own source code.
Or do you have multiple versions of your sources (e.g. one in vhdl,
and another in verilog)?
Well, the libs are also available in two HDLs, so you could do
multilingual cross-simulation.
e.g. vhdl soure with vhdl lib ,
verilog source with vhdl lib,
vhdl source with verilog lib,
verilog source with verilog lib


Have a nice simulation
Eilert

 

[russ]

Can't you argue that gate level simulation in ISE is verified by the
actual hardware? If the hardware behaves the same as the gate level
simulation doesn't that mean something?

Then you can restrict the two tool sets as a cross check of RTL
behaviour.

regards
Alan

That solution is our Plan A, and might be accepted. I'm working on plan
B, just in case. Plan C is to get the tool qualified, which will be
expensive. Then there is Plan 9...

 

[russ]

Sounds like your customer is the typical military type with his head
up his ass.

-a

The guy with the big checkbook never has his head up his ass. You play
by his rules or find another game.

 

[russ]

very good, there isn't enough humour on this newsgroup

Russ, I would suggest you contact your DER and discuss the tools issue
before going on a tangent with GHDL.

Hans
www.ht-lab.com

Thanks, that is under discussion. The object here is to present
"alternatives" with costs. Also thrown into the mix is obsolescence
planing and robustness.
My root reason for this post is to propose two independent low-cost
means of verifying the design. GHDL isn't a reqirement cast in stone.

 

[aloque]

The way I do to use unisims with ghdl:

Library UNISIM;
use UNISIM.vcomponents.all;

In project path I make a dir called unisim and then copy all files of vhdl/src/unisims in ISE install path in my case /opt/Xilinx92i/vhdl/src/unisims/ for 9.2i version and /opt/Xilinx/10.1/ISE/vhdl/src/unisims for 10.1.

mkdir unisim
cp /opt/Xilinx/10.1/ISE/vhdl/src/unisims/* unisim/

Then compile the unisim librarys with:

k@klap:~/vhdl$ ghdl -a --work=unisim --ieee=synopsys -fexplicit unisim/unisim_VCOMP.vhd
k@klap:~/vhdl$ ghdl -a --work=unisim --ieee=synopsys -fexplicit unisim/unisim_SMODEL.vhd
k@klap:~/vhdl$ ghdl -a --work=unisim --ieee=synopsys -fexplicit --warn-no-vital-generic unisim/unisim_VITAL.vhd
unisim/unisim_VITAL.vhd:150882:18:warning: universal integer bound must be numeric literal or attribute
unisim/unisim_VITAL.vhd:182323:57: variable "write_a_write_b" is not visible here
unisim/unisim_VITAL.vhd:182324:57: variable "read_a_write_b" is not visible here
unisim/unisim_VITAL.vhd:182325:57: variable "write_a_read_b" is not visible here
unisim/unisim_VITAL.vhd:182326:57: variable "write_b_write_a" is not visible here
unisim/unisim_VITAL.vhd:182327:57: variable "read_b_write_a" is not visible here
unisim/unisim_VITAL.vhd:182328:57: variable "write_b_read_a" is not visible here
/usr/lib/ghdl/bin/ghdl: compilation error

We need to comment the lines (182323,1823234, 182325, 182326, 182327, 182328) on file unisim_VITAL.vhd:

variable Write_A_Write_B : memory_collision_type := Write_A_Write_B;
variable Read_A_Write_B : memory_collision_type := Read_A_Write_B;
variable Write_A_Read_B : memory_collision_type := Write_A_Read_B;
variable Write_B_Write_A : memory_collision_type := Write_B_Write_A;
variable Read_B_Write_A : memory_collision_type := Read_B_Write_A;
variable Write_B_Read_A : memory_collision_type := Write_B_Read_A;

If we try to repeat the last command we are going to get the reference to others lines, then when we open the unisim_VITAL.vhd its more easy search for the line variable Write_A_Write_B: memory_collision_type:= etc. and comment this line and next 5.

On 9.2i version lines are (176564, 176565, 176566, 176567, 176568, 176569) and (188630,188631,188632, 188633, 188634, 188635).

Now you are going to be able to compile your project with:

ghdl -a --ieee=synopsys -Punisim -fexplicit

I think that is the same with simprims librarys that are in the same path that unisims.

I add a simple example of a RAM using unisims

I found the next url:

armadeus.com/wiki/index.php?title=How_to_simulate_post_synthesis_and_post_place_%26_route_design_with_GHDL