Index Array (Yet Another Question)

Discussion in 'VHDL' started by Filipa, Nov 26, 2008.

  1. Filipa

    Filipa Guest

    Hi,

    I found several questions posted about array indexing but I am still
    confused on how can I solve my problem.
    I have a memory array that I want to index with a hot-one address.

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

    entity memory is
    generic( addr_width : integer := 5;
    data_width : integer := 4);
    port(
    Q : out std_logic_vector(data_width - 1 downto 0 );
    R_ADR : in std_logic_vector(2**addr_width - 1 downto 0);
    W_ADR : in std_logic_vector(2**addr_width - 1 downto 0);
    D : in std_logic_vector(data_width - 1 downto 0 );
    W : in std_logic;
    R : in std_logic;
    ME : in std_logic;
    CLK : in std_logic
    );
    end memory;


    architecture synth_mem of memory is
    type mem_array is array (std_ulogic range <>) of std_logic_vector
    (data_width - 1 downto 0 );
    signal ram : mem_array(2**addr_width - 1 downto 0);

    -- function hot_to_int(hot: std_logic_vector(2**addr_width - 1
    downto 0)) return integer is
    -- variable conv : integer := 0;
    -- begin
    -- for i in 0 to 2**addr_width - 1 loop
    -- if hot(i) = '1' then
    -- conv := i;
    -- end if;
    -- end loop;
    -- return conv;
    -- end hot_to_int;

    begin
    -- process (ME, CLK)
    -- begin
    -- if ME = '1' then
    -- Q <= (others => '1');
    -- elsif CLK'event and CLK = '1' then
    -- if R = '1' then
    -- Q <= ram(R_ADR);
    -- else
    -- Q <= (others => '1');
    -- end if;
    ---- if W = '1' then
    ---- ram(W_ADR) <= D;
    ---- end if;
    -- end if;
    -- end process;

    ram(W_ADR) <= D when (W = '1' and CLK = '0');
    Q <= ram(R_ADR) when (R = '1' and CLK = '0');

    end synth_mem;
    Filipa, Nov 26, 2008
    #1
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