Inferring RAM from array of records

Discussion in 'VHDL' started by jtw, Mar 9, 2006.

  1. jtw

    jtw Guest

    A coworker asked me if I knew of a problem with synthesis tools inferring
    RAM (Xilinx is the target) from an array of records, versus an array of
    std_logic_vector. He was using XST; I haven't had a chance to try
    Synplify.

    JTW
    jtw, Mar 9, 2006
    #1
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  2. jtw wrote:
    > A coworker asked me if I knew of a problem with synthesis tools inferring
    > RAM (Xilinx is the target) from an array of records, versus an array of
    > std_logic_vector.


    I have found that inference is not
    sensitive to vector type if the
    template matches functionally.
    Try it and see.

    -- Mike Treseler
    Mike Treseler, Mar 9, 2006
    #2
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