INFO:Xst:1304 -- precise definition anyone?

Discussion in 'VHDL' started by Joseph, May 6, 2005.

  1. Joseph

    Joseph Guest

    Hello,

    I am using VHDL and XST. I read some all the older threads that
    mention the info/warning:

    INFO:Xst:1304 - Contents of register <slv_ip2bus_data> in unit
    <user_logic> never changes during circuit operation. The register is
    replaced by logic.

    And I still don't have a clear idea of why I am getting this problem in
    my code. Rather than have you debug my code (though I can post if
    helpful), can someone describe, in as much detail as you can stand,
    what causes this message? I have no doubt it is my poor coding, but
    hope a clear description can help me tidy things up. I think I am
    using good FSM style (clk process to change state, comb process to get
    next state, output process based on current state).

    Any advice or pointers to documentation on this message appreciated...

    Joey
     
    Joseph, May 6, 2005
    #1
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  2. Joseph

    Joseph Guest

    It seems that posting here (or the fpga group) clears my head (I think
    I've answerd myself 3 times now within 24hrs of posting)... figured out
    that my state machine setup was essentially correct, but I was not
    clocking my registers, sort of assumed they would be updated (and
    'saved') in the output process when I said stuff like:

    my_ff <= my_ff and other_signal;

    but since this process was combinational, my_ff wasn't ever going to
    become a real FF. I guess these are the growing pains of transforming
    from a programmer to a HW designer. Thanks to anyone who read this
    thread and thought about it at all (sorry for my ramblings). If any of
    my analysis is flawed, please set me straight.

    Joey
     
    Joseph, May 7, 2005
    #2
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  3. Hi Joey,

    > It seems that posting here (or the fpga group) clears my head (I think
    > I've answerd myself 3 times now within 24hrs of posting)... figured out
    > that my state machine setup was essentially correct, but I was not
    > clocking my registers, sort of assumed they would be updated (and
    > 'saved') in the output process when I said stuff like:
    >
    > my_ff <= my_ff and other_signal;
    >
    > but since this process was combinational, my_ff wasn't ever going to
    > become a real FF. I guess these are the growing pains of transforming
    > from a programmer to a HW designer.


    Is it possible for you to send me a snippet of the failing and the working
    code? I'm currently writing a one-day training called "VHDL design for
    software engineers" and would like to see if this is a thinko I haven't
    covered yet.

    Don't send code to the address specified in the header. Send it to
    [myfirstname].[mylastname] at gmail dot com. Oh, and don't try to pronounce
    my last name. It may hurt your tongue.

    Best regards,


    Ben Twijnstra
     
    Ben Twijnstra, May 8, 2005
    #3
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