Init RAM component

Discussion in 'VHDL' started by hilal, Mar 13, 2008.

  1. hilal

    hilal

    Joined:
    Mar 13, 2008
    Messages:
    5
    Hi, I am having a problem with initializing BlockSelect ram that I use through component instantiation and not through IP CORE.

    I instantiate it like this:

    Code:
    RAMB16_S18_S18_inst : RAMB16_S18_S18
       generic map (
          INIT_A => X"00000", --  Value of output RAM registers on Port A at startup
          INIT_B => X"00000", --  Value of output RAM registers on Port B at startup
          SRVAL_A => X"00000", --  Port A ouput value upon SSR assertion
          SRVAL_B => X"00000", --  Port B ouput value upon SSR assertion
          WRITE_MODE_A => "READ_FIRST",
          WRITE_MODE_B => "READ_FIRST",
          SIM_COLLISION_CHECK => "WARNING",
          -- The follosing INIT_xx declarations specify the intiial contents of the RAM
          -- Address 0 to 255
          	INIT_00=> X"...", 
    	INIT_01=> X"...", 
            ....
       )
       port map (
          DOA => buff_douta,      -- Port A 16-bit Data Output
          DOB => buff_doutb,      -- Port B 16-bit Data Output
          DOPA => open,    -- Port A 2-bit Parity Output
          DOPB => open,    -- Port B 2-bit Parity Output
          ADDRA => addra,  -- Port A 10-bit Address Input
          ADDRB => addrb,  -- Port B 10-bit Address Input
          CLKA => clk_falling,    -- Port A Clock
          CLKB => clk_falling,    -- Port B Clock
          DIA => dina,      -- Port A 16-bit Data Input
          DIB => dinb,      -- Port B 16-bit Data Input
          DIPA => "00",    -- Port A 2-bit parity Input
          DIPB => "00",    -- Port-B 2-bit parity Input
          ENA => '1',      -- Port A RAM Enable Input
          ENB => '1',      -- PortB RAM Enable Input
          SSRA => '0',    -- Port A Synchronous Set/Reset Input
          SSRB => '0',    -- Port B Synchronous Set/Reset Input
          WEA => wea,      -- Port A Write Enable Input
          WEB => web       -- Port B Write Enable Input
       ); 
    
    The problem I have is that many components use their own BlockSelect ram, and I want to instantiate each with a different 'image', so can I put the 'image' on a file? Or do you have another solution? :hmmmm:

    thank you in advance
    hilal, Mar 13, 2008
    #1
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  2. hilal

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Use a COE file

    Your allowed to initialize a Block RAM with a COE-file which contain ASCII code of your choiche.

    Jeppe
    jeppe, Mar 14, 2008
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  3. hilal

    hilal

    Joined:
    Mar 13, 2008
    Messages:
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    but CEO is only when you use the IP Core Generator and not component instantiation.
    hilal, Mar 14, 2008
    #3
  4. hilal

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Yes

    If you study the Picoblaze can you find a tool which convert the assembler code to a ROM.VHD file - not what your need - but it shows how it could be done.

    Some of my students claim to have a program which could modify the bit-file directly.
    The trick must be to make a design with a "wellknown" content of a blockRAM and then use the WINHEX program to find the region in the bit-file.
    Then you must make program which could read a bit-file and change the blockRAM part with the new content.
    Sounds easy ;-)

    Jeppe
    Last edited: Mar 14, 2008
    jeppe, Mar 14, 2008
    #4
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