Initial Value at start of process

Discussion in 'VHDL' started by Roger Planger, Oct 5, 2004.

  1. Hi

    I have declared a Type with different states as you can see.

    type STATE_TYPE is (IDLE, STLDA, STLDB, ADDS, FINISHS);

    My question now is, how can I say my VHDL compiler that when he starts we
    are in the IDLE State? Afterwards
    it is easy to jump from one state to another.

    Thanks for any hints

    R
     
    Roger Planger, Oct 5, 2004
    #1
    1. Advertising

  2. Sorry for this stupid question, I figured it out in the meantime :)

    Cheers
     
    Roger Planger, Oct 5, 2004
    #2
    1. Advertising

  3. > Sorry for this stupid question, I figured it out in the meantime :)

    Actually, it is not. Meantime I was sure that initialization during
    declaration
    signal STATE: TENUM := IDLE;

    is intended for simulation while synthesis style must be:

    process(CLK, RST)
    if ASYNC_RST and RST = '1'
    STATE <= IDLE;
    else if Rising_Edge(CLK)
    if not ASYNC_RST and RST = '1' then
    STATE <= IDLE;

    It turns out that the redundancy is needed as Xilinx FPGA loader will
    initialize FFs to the values found in the declaration section.
     
    valentin tihomirov, Oct 5, 2004
    #3
  4. Hi

    THanks for this hint, my problem is that I dont have a reset signal at the
    moment. Therefore I want my State Machine to
    be in the Idle state right from the beginning. It looks like that I have to
    add this reset port to my IP

    cheers

    Roger

    "valentin tihomirov" <> wrote in message
    news:...
    >> Sorry for this stupid question, I figured it out in the meantime :)

    >
    > Actually, it is not. Meantime I was sure that initialization during
    > declaration
    > signal STATE: TENUM := IDLE;
    >
    > is intended for simulation while synthesis style must be:
    >
    > process(CLK, RST)
    > if ASYNC_RST and RST = '1'
    > STATE <= IDLE;
    > else if Rising_Edge(CLK)
    > if not ASYNC_RST and RST = '1' then
    > STATE <= IDLE;
    >
    > It turns out that the redundancy is needed as Xilinx FPGA loader will
    > initialize FFs to the values found in the declaration section.
    >
    >
     
    Roger Planger, Oct 6, 2004
    #4
  5. Roger Planger wrote:
    > THanks for this hint, my problem is that I dont have a reset signal at the
    > moment. Therefore I want my State Machine to
    > be in the Idle state right from the beginning. It looks like that I have
    > to add this reset port to my IP


    I believe that within an FPGA you can make sure the design starts in a
    defined state. For an ASIC however this is not possible. As such it is good
    practice to place a reset within your design, and if I may be so bold:
    please make it a synchronous reset i.s.o. an asynchronous one...

    Regards,

    Pieter Hulshoff
     
    Pieter Hulshoff, Oct 6, 2004
    #5
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Marek Ponca

    Initial value on ports

    Marek Ponca, Aug 8, 2003, in forum: VHDL
    Replies:
    0
    Views:
    2,741
    Marek Ponca
    Aug 8, 2003
  2. Replies:
    3
    Views:
    1,019
  3. Lucas Tam
    Replies:
    0
    Views:
    522
    Lucas Tam
    Jun 17, 2005
  4. PGK
    Replies:
    1
    Views:
    532
  5. jpock76
    Replies:
    0
    Views:
    627
    jpock76
    Aug 23, 2010
Loading...

Share This Page