Initial value on ports

Discussion in 'VHDL' started by Marek Ponca, Aug 8, 2003.

  1. Marek Ponca

    Marek Ponca Guest

    hi,

    is there some way how to define an initial value of an output in verilog
    ?

    ....something similar as initial value of a signal in VHDL:
    a : std_logic := '1';


    There is a need for mixed-signal simulation, to have defined digital
    initial values before the simulation starts. It would help the analog
    simulator
    to define the initial conditions.

    Thanks,
    Marek
    Marek Ponca, Aug 8, 2003
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Roger Planger

    Initial Value at start of process

    Roger Planger, Oct 5, 2004, in forum: VHDL
    Replies:
    4
    Views:
    4,626
    Pieter Hulshoff
    Oct 6, 2004
  2. Replies:
    3
    Views:
    977
  3. DC Gringo

    dropdownlist initial value

    DC Gringo, Mar 3, 2004, in forum: ASP .Net
    Replies:
    3
    Views:
    3,777
    DC Gringo
    Mar 3, 2004
  4. PGK
    Replies:
    1
    Views:
    514
  5. mreister
    Replies:
    1
    Views:
    3,108
    mreister
    May 25, 2010
Loading...

Share This Page