Initialization

Discussion in 'VHDL' started by spartan, May 24, 2004.

  1. spartan

    spartan Guest

    Hi everybody,
    In the following code I need to (and have to) initialize "sum1" and "sum2"
    signals. the first idea was to initialize it when rst='1' but I got the
    synthesis failure because of this warning: "Multi-source in Unit <test> on
    signal <sum1_8> not replaced by logic. Signal is stuck at GND". Of course
    I am using ISE 6.02.
    Any idea what is wrong with the code? Or how I can initialize "sum1" and
    "sum2"?
    Thanks a lot.

    Library IEEE;
    Use ieee.std_logic_1164.all;
    Use ieee.std_logic_arith.all;

    entity test is
    Port ( clk,rst :in std_logic;
    I :in std_logic_vector(7 downto 0);
    w1,w2 :eek:ut std_logic_vector(8 downto 0));
    end test;

    architecture Behavioral of test is
    signal w1i, w2i : signed(8 downto 0);
    signal sum1,sum2 : signed(8 downto 0);
    begin
    process(I,w1i,w2i)
    constant alpha : signed(8 downto 0):= "010000000";
    variable IC : signed(7 downto 0);
    variable d1,d2,ad1,ad2 : signed(8 downto 0);
    variable prod1, prod2 : signed(17 downto 0);
    variable prodt1, prodt2: signed(8 downto 0);
    begin
    IC := signed(I);
    d1 := conv_signed(IC,9) - conv_signed(w1i,9);
    d2 := conv_signed(IC,9) - conv_signed(w2i,9);
    ad1:= abs(d1);
    ad2:= abs(d2);
    if ad1 <= ad2 then
    prod1 := alpha * d1;
    prodt1:= prod1 (16 downto 8);
    sum1 <= w1i+ prodt1;
    else
    prod2 := alpha * d2;
    prodt2:= prod2 (16 downto 8);
    sum2 <= w2i+ prodt2;
    end if;
    end process;


    process(clk,rst)
    begin
    if clk'event and clk='1' then
    if rst='1' then
    w1i<= "000000000";
    w2i<= "000001010";
    sum1<= "000000000";
    sum2<= "000001010";
    else
    w1i <= sum1;
    w2i <= sum2;
    end if;
    end if;
    end process;
    w1<= std_logic_vector(w1i);
    w2<= std_logic_vector(w2i);
    end Behavioral;
     
    spartan, May 24, 2004
    #1
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  2. spartan

    deep Guest

    You are using two proceses...and assigning some values to sum1 and sum2 in
    both ...this should be avoided...try assigning values in one process
    only...

    --deep
     
    deep, May 24, 2004
    #2
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  3. Hello,

    "deep" <> wrote:
    > You are using two proceses...and assigning some values to sum1 and sum2 in
    > both ...this should be avoided...try assigning values in one process


    It is not only "to be avoided", this is _evil_ until you know exactly
    what you are doing.
    This construct leads to internal tristate buses which are very nasty
    even if you intended to use them.

    BTW initialisations in the VHDL-code are only for simulations, they
    won't be synthesised.
    The OP should rewrite the code in one sequential process with
    initialisations done with reset.

    bye Thomas
     
    Thomas Stanka, May 24, 2004
    #3
  4. On Mon, 24 May 2004 01:41:52 -0400, deep <> wrote:

    > You are using two proceses...and assigning some values to sum1 and sum2
    > in
    > both ...this should be avoided...try assigning values in one process
    > only...
    >
    > --deep
    >



    One way to avoid this kind of mistake is to clearly separate combinatorial
    and sequential processes.

    Example:

    signal sum_present : signed(8 downto 0);
    signal sum_next : signed(8 downto 0);

    -- sequential process, describing flip flops
    process(Clk, Rst)
    begin
    if Clk'event and Clk='1' then
    if rst='1' then
    sum_present <= "000000000";
    else
    sum_present <= sum_next;
    end if;
    end if;
    end process;

    -- combinatorial process, describing logic between flip flops
    process(sum_present, other_signals)
    begin
    if ... then
    sum_next <= function(sum_present, other_signals);
    ...
    else
    sum_next <= ...
    ...
    end if;
    end process;
     
    Samuel Fuhrer, May 24, 2004
    #4
  5. spartan

    ivero Guest

    Initialize it when rst='1' but in the first process you write.

    And one more thing, if signal rst is synchronous you probably do not want to
    put it in the sensitivity list of the process (the second you write).

    "spartan" <> escribió en el mensaje
    news:...
    > Hi everybody,
    > In the following code I need to (and have to) initialize "sum1" and "sum2"
    > signals. the first idea was to initialize it when rst='1' but I got the
    > synthesis failure because of this warning: "Multi-source in Unit <test> on
    > signal <sum1_8> not replaced by logic. Signal is stuck at GND". Of course
    > I am using ISE 6.02.
    > Any idea what is wrong with the code? Or how I can initialize "sum1" and
    > "sum2"?
    > Thanks a lot.
    >
    > Library IEEE;
    > Use ieee.std_logic_1164.all;
    > Use ieee.std_logic_arith.all;
    >
    > entity test is
    > Port ( clk,rst :in std_logic;
    > I :in std_logic_vector(7 downto 0);
    > w1,w2 :eek:ut std_logic_vector(8 downto 0));
    > end test;
    >
    > architecture Behavioral of test is
    > signal w1i, w2i : signed(8 downto 0);
    > signal sum1,sum2 : signed(8 downto 0);
    > begin
    > process(I,w1i,w2i)
    > constant alpha : signed(8 downto 0):= "010000000";
    > variable IC : signed(7 downto 0);
    > variable d1,d2,ad1,ad2 : signed(8 downto 0);
    > variable prod1, prod2 : signed(17 downto 0);
    > variable prodt1, prodt2: signed(8 downto 0);
    > begin
    > IC := signed(I);
    > d1 := conv_signed(IC,9) - conv_signed(w1i,9);
    > d2 := conv_signed(IC,9) - conv_signed(w2i,9);
    > ad1:= abs(d1);
    > ad2:= abs(d2);
    > if ad1 <= ad2 then
    > prod1 := alpha * d1;
    > prodt1:= prod1 (16 downto 8);
    > sum1 <= w1i+ prodt1;
    > else
    > prod2 := alpha * d2;
    > prodt2:= prod2 (16 downto 8);
    > sum2 <= w2i+ prodt2;
    > end if;
    > end process;
    >
    >
    > process(clk,rst)
    > begin
    > if clk'event and clk='1' then
    > if rst='1' then
    > w1i<= "000000000";
    > w2i<= "000001010";
    > sum1<= "000000000";
    > sum2<= "000001010";
    > else
    > w1i <= sum1;
    > w2i <= sum2;
    > end if;
    > end if;
    > end process;
    > w1<= std_logic_vector(w1i);
    > w2<= std_logic_vector(w2i);
    > end Behavioral;
    >
     
    ivero, May 24, 2004
    #5
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