Initializing a signal externally

Discussion in 'VHDL' started by jjsandoval1962@aol.com, Jan 16, 2009.

  1. Guest

    How can one initialize a signal inside an entity from the outside
    world?

    I have an Entity named "Spi_slave" and I have the need to initialize
    it at any time during my simulation run from my testbench without
    having to use a system clock or reset.

    In Verilog I would easily accomplish this by using a hierarchical call
    such as:

    Spi_slave.mem_index = 0;

    Regards,
    Jose

    =============this is the code==================================
    signal mem_index: std_logic_vector (07 downto 00):= (others
    =>'0');

    begin -- beginning of behav

    main: process
    begin

    for i in 1 to 8
    loop
    wait until spi_clk_fixed'event and spi_clk_fixed = '1' and
    spi_clk_fixed'last_value = '0';
    data_in <= data_in( 06 downto 00 ) & mosi;
    end loop;

    wait for 1 * PERIOD;
    mem(conv_integer(mem_index)) <= data_in;
    wait for 1 * PERIOD;
    mem_index <= mem_index + 1;
    print("... SPI: << data is >> "& hstr(data_in)& "h");


    end process main;

    end behav;
     
    , Jan 16, 2009
    #1
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  2. wrote:
    > How can one initialize a signal inside an entity from the outside
    > world?
    >
    > I have an Entity named "Spi_slave" and I have the need to initialize
    > it at any time during my simulation run from my testbench without
    > having to use a system clock or reset.



    Because that entity is a not a synthesis model anyway
    I could either package the signal mem_index,
    or make it an input port.

    -- Mike Treseler
     
    Mike Treseler, Jan 16, 2009
    #2
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