Input Delay and Hold Time

Discussion in 'VHDL' started by Anand P Paralkar, Jan 16, 2004.

  1. Hi,

    I was looking up the man pages for the synthesis directive
    set_input_delay (in Synopsys DC).

    The man page says:

    Specifies the path delay. The
    delay_value must be in units consistent
    with the technology library used during
    optimization. The delay_value represents
    the amount of time the signal is
    available after a clock edge. This
    usually represents a combinational path
    delay from the clock pin of a register.

    If input delay is "the amount of time the signal is available after a
    clock edge", then:

    1. Is "input delay" different from "hold time"?

    2. If these are two different parameters, what exactly is the
    difference?

    Thanks,
    Anand
     
    Anand P Paralkar, Jan 16, 2004
    #1
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  2. Anand P Paralkar

    David Jones Guest

    In article <>,
    Anand P Paralkar <> wrote:
    >If input delay is "the amount of time the signal is available after a
    >clock edge", then:
    >
    > 1. Is "input delay" different from "hold time"?
    >
    > 2. If these are two different parameters, what exactly is the
    > difference?


    Consider two blocks A and B. An output FOO from A is an input to B.

    You are synthesizing block B. You have no control over block A.

    The specs for block A state that signal FOO is valid 2.3 ns after
    the rising edge of the clock.

    When Synopsys does its timing analysis, it needs to know that any
    path starting from FOO has already experienced 2.3 ns of delay
    from the clock. The set_input_delay statement conveys this
    information.

    Hold time is different. You usually don't specify this (it
    is specified in the cell library, and Synopsys will conform
    to the hold time of the devices it chooses).
     
    David Jones, Jan 16, 2004
    #2
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  3. In article <>, says...
    > Hi,
    >
    > I was looking up the man pages for the synthesis directive
    > set_input_delay (in Synopsys DC).
    >
    > The man page says:
    >
    > Specifies the path delay. The
    > delay_value must be in units consistent
    > with the technology library used during
    > optimization. The delay_value represents
    > the amount of time the signal is
    > available after a clock edge. This
    > usually represents a combinational path
    > delay from the clock pin of a register.
    >
    > If input delay is "the amount of time the signal is available after a
    > clock edge", then:
    >
    > 1. Is "input delay" different from "hold time"?
    >
    > 2. If these are two different parameters, what exactly is the
    > difference?


    Input delay tells DC how long after the clock before an input becomes valid.
    Hold time is the amount of time after the clock the value of a signal (usually
    an output) does not change.

    --
    Rich Iachetta
     
    Richard Iachetta, Jan 16, 2004
    #3
  4. Anand P Paralkar

    j Guest

    Watch the hold times on the input to CHIP. If no PLL to cancel insertion
    delay, this will bite you, if not taken into account.

    "Richard Iachetta" <> wrote in message
    news:...
    > In article <>, says...
    > > Hi,
    > >
    > > I was looking up the man pages for the synthesis directive
    > > set_input_delay (in Synopsys DC).
    > >
    > > The man page says:
    > >
    > > Specifies the path delay. The
    > > delay_value must be in units consistent
    > > with the technology library used during
    > > optimization. The delay_value represents
    > > the amount of time the signal is
    > > available after a clock edge. This
    > > usually represents a combinational path
    > > delay from the clock pin of a register.
    > >
    > > If input delay is "the amount of time the signal is available after a
    > > clock edge", then:
    > >
    > > 1. Is "input delay" different from "hold time"?
    > >
    > > 2. If these are two different parameters, what exactly is the
    > > difference?

    >
    > Input delay tells DC how long after the clock before an input becomes

    valid.
    > Hold time is the amount of time after the clock the value of a signal

    (usually
    > an output) does not change.
    >
    > --
    > Rich Iachetta
     
    j, Jan 17, 2004
    #4
  5. > Specifies the path delay. The
    > delay_value must be in units consistent
    > with the technology library used during
    > optimization. The delay_value represents
    > the amount of time the signal is
    > available after a clock edge. This
    > usually represents a combinational path
    > delay from the clock pin of a register.
    >
    > If input delay is "the amount of time the signal is available after a
    > clock edge", then:
    >
    > 1. Is "input delay" different from "hold time"?



    Minimum Timing path between 2 FFs is : 1-st FF hold time +
    interconnect delay + 2-nd FF setup time.
    Minimum Timing path between 2 sequential networks is : 1-st network
    output delay + interconnect delay + 2-nd network (clock period - input
    delay).

    The following picture illustrates it:

    --- -----
    N1 | | N2
    | |
    --- -----
    Interconnect d
    <---|<------------>|----->
    ---------------------------------
    1-st network 2-nd network
    output delay (clk period -input delay)
    (network "hold") (network "setup")

    Synopsys defines input delay to be opposite to network's "setup time".
    Assuming that we have 1 clock period for timing path between 2
    networks,
    input delay is defined as "external to setup" timing, i.e. clock
    period - "network setup"


    Giving 0 delay for network interconnect, your statement becomes almost
    true:

    Input delay of network N2 equals to Output delay ("hold") of the
    network N1.

    2 reasons make your statement "almost true":
    1. In reality interconnect delay > 0
    2. We are speaking about setup and hold times of 2 different networks.


    Regards,
    Alexander Gnusin
     
    Alexander Gnusin, Jan 20, 2004
    #5
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