Debashish said:
Hi guys,
This is my 1st message to the group.I work as a VHDL programmer. I
have a hard time in analyzing the hierarchy and then tracing the
signals i.e. where a signal is generated and to which component it
goes to. Now i am doning...by personally vewing...or verifying the
code. Will some help me to find a tool that automatically generates
this kinda report thus saving enormous amount of precious time..
To quickly find the files and line numbers,
if you have the system command "grep" available,
from the source directory you can say:
grep -n my_sig_name *.vhd
For maintainable wires, make your top level
entity out of direct instances with named
associations. Like this:
----------------------------------------------------------------------------
-- Component instances are direct to eliminate component
-- declarations. The only component that might need indirect
-- instances is the device level entity because we might want
-- to configure the top level for a source code architecture and or
-- for a timing netlist architecture from quartus. Since these are
-- all internal entities, only the source architectures will ever
-- be needed.
----------------------------------------------------------------------------
hdlc_1 : entity work.hdlc
port map (reset => reset, -- [in]
rx_clk => rx_clk, -- [in]
rx_clk_dis => rx_clk_dis, -- [in]
sys_clk => sys_clk, -- [in]
bitstream => bitstream, -- [in]
crc32not16 => crc32not16, -- [in]
octet_valid => octet_valid_wire, -- [out]
octet_count => octet_count_wire, -- [out]
eop => eop_wire, -- [out]
sop => sop_wire, -- [out] -- not used
octet_out => octet_out_wire, -- [out]
error_code => error_code); -- [out]
hdlc2packet_1 : entity work.hdlc2packet
port map (reset => reset, -- [in]
clk => sys_clk, -- [in]
octet_in => octet_out_wire, -- [in]
octet_valid => octet_valid_wire, -- [in]
octet_count => octet_count_wire, -- [in]
eop => eop_wire, -- [in]
packet_bus => packet_bus,
word_valid => word_valid, -- [out]
packet_start => packet_start, -- [out]
packet_end => packet_end, -- [out]
end_ona_byte => end_ona_byte); -- [out]
--- etc, etc
----------------------------------------------
Then all the wires and ports are in one file.
All you need is an editor search to check or fix them.
Use some suffix like _s or _wire on wire signals so you can tell
port to port connections from wired connections.
There are graphical hierarchy viewers available,
but I find these ponderously slow for large designs.
Note that emacs vhdl-mode will do a lot of this work for you.
-- Mike Treseler