Instantiation of verilog component

Discussion in 'VHDL' started by sadann, Feb 27, 2008.

  1. sadann

    sadann

    Joined:
    Feb 27, 2008
    Messages:
    1
    Can anybody direct me to links that explain how to instantiate a verilog component into a vhdl testbench?
     
    sadann, Feb 27, 2008
    #1
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