Int to std_logic_vector conversion problem

Discussion in 'VHDL' started by Woodrow, May 13, 2009.

  1. Woodrow

    Woodrow

    Joined:
    May 13, 2009
    Messages:
    1
    Hi everyone, I'm new to this forum and relatively new to VHDL.

    I am having trouble converting an integer to a std_logic_vector array. I am reading integer values from a text file, and am attempting to convert them to the std_logic_vector data type using 32 bits to represent them. I want to have a std_logic_vector array of 1152 samples long where every sample is 32 bits wide.

    I can get the conversion to work, however it limits the conversion to 8 bits for some reason. Is there a method or alternative function to "conv_std_logic_vector" that will perform the conversion using 32 bits?

    Here is my code used to read from the textfile:

    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_arith.all; -- obsolete?
    use STD.textio.all;
    use IEEE.numeric_std.all;
    use WORK.my_package.all;

    --type intarray is array (0 to 1151) of integer;

    entity ReadInput is
    port( Output : out std_array(1151 downto 0);
    Enable : in std_logic;
    N : out integer;
    Res : out boolean); --(8 downto 1));
    end entity ReadInput;

    architecture behavioral of ReadInput is
    begin

    io_process: process(Enable) is

    file infile: TEXT open read_mode is "input.txt";
    variable linein: line;
    variable value: integer:= 0;
    variable GOOD: boolean;
    variable Counter: integer:= 0;

    begin
    if(rising_edge(Enable)) then
    while (not endfile (infile)) loop
    readline(infile, linein);
    read(linein, value, Good);
    Output(1151 - Counter)<= conv_std_logic_vector(conv_signed(value,32),32);
    Counter:= Counter + 1;
    N <= Counter;
    Res <= Good;
    end loop;
    end if;
    end process io_process;
    end architecture behavioral;


    ** I have used a package containing a data type called "std_array" where I have defined the data type as:

    TYPE std_array IS ARRAY (integer RANGE <>) OF std_logic_vector(32-1 DOWNTO 0);

    Any help would be greatly appreciated. I cant seem to find where I'm going wrong here.

    Thanks
     
    Woodrow, May 13, 2009
    #1
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